Parallel Multi-Ramp Merged Comparator ADC for Image Sensor Noise Reduction
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Solution Overview
Problem
Current image sensors require significant time, power, and chip area to effectively reduce noise using multisampling in ramp ADC, compromising performance and efficiency in high-speed applications.
Innovation Solution
The implementation of a parallel multi-ramps merged comparator ADC, which uses a single comparator with multiple inputs to receive and compare pixel data signals with differently valued or timed ramp signals, emulating correlated multi-sampling to reduce noise while minimizing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multisampling in ramp ADC is used to reduce noise, then noise reduction is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple ramp ADC operations into a single integrated circuit that performs correlated multi-sampling. The merged comparator ADC combines multiple ramp generators and comparators into one unified structure that can simultaneously perform multiple sampling operations, reducing the overall power consumption compared to separate multisampling circuits while maintaining noise reduction effectiveness.
Solution Approach 2:
The merged comparator ADC is designed to perform multiple functions within a single circuit block. It can perform correlated multi-sampling, standard ramp ADC conversion, and noise filtering operations simultaneously, making the circuit universal and reducing the need for additional dedicated noise reduction circuits that would increase power consumption.
2Measurement precision
If multisampling in ramp ADC is used to reduce noise, then noise reduction is improved, but chip area increases
Solution Approach 1:
The patent merges multiple ramp ADC operations into a single integrated circuit that performs correlated multi-sampling. The merged comparator ADC combines multiple ramp generators and comparators into one unified structure that can simultaneously perform multiple sampling operations, reducing the overall power consumption compared to separate multisampling circuits while maintaining noise reduction effectiveness.
Solution Approach 2:
The merged comparator ADC employs a nested structure where multiple ramp generators are hierarchically organized within a single comparator unit. The circuit nests multiple sampling operations within one another, allowing the first ramp signal, second ramp signal, and subsequent ramp signals to be processed through a shared comparator infrastructure, thereby reducing the total chip area required for noise reduction functionality.
3Measurement precision
If multisampling in ramp ADC is used to reduce noise, then noise reduction is improved, but conversion time increases
Solution Approach 1:
The merged comparator ADC implements periodic ramp signal generation where multiple ramp signals are generated in a cyclic sequence. The circuit alternates between generating first ramp signals, second ramp signals, and subsequent ramp signals in periodic intervals, allowing noise reduction through correlated sampling without requiring all samples to be taken sequentially, thus reducing total conversion time.
Solution Approach 2:
The merged comparator ADC maintains continuous operation by overlapping the generation and comparison of multiple ramp signals. While one ramp signal is being compared, the next ramp signal is already being generated, ensuring that the useful action of noise reduction continues without interruption or idle time between sampling operations.
Data Source
AI summary
A method of reducing noise in an image sensor using a parallel multi-ramps merged comparator analog-to-digital converter (ADC) starts with a pixel array capturing image data. The pixel array includes pixels to generate pixel data signals, respectively. An ADC circuitry acquires the pixel data signals. The ADC circuitry includes ADC circuits. Each of the ADC circuits includes a comparator and latches. The comparator includes a multi-input first stage. The comparator in each ADC circuit compares one of the pixel data signals to ramp signals received from a logic circuitry to generate comparator output signals. The latches in each ADC circuit latches the counter based on the comparator output signals, respectively, to generate ADC outputs. Other embodiments are described.