Parallel Multiplexer Architecture for High-Speed Data Transmission
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Solution Overview
Problem
Current Electrical Time-Division Multiplexing (ETDM) technologies are limited to 80 gigabits per second, failing to meet the growing need for higher data transmission rates due to limitations in materials and technologies used.
Innovation Solution
An electronic circuit that doubles the multiplexing capabilities by generating four primary signals associated with specific binary states and using electronic selection means to produce a final multiplexed signal, allowing for higher data rates using less expensive technologies, applicable to both ETDM and Optical Time-Division Multiplexing (OTDM) technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ETDM technologies are used, then the implementation cost is reduced, but the data transmission rate is limited to 80 gigabits per second
Solution Approach 1:
The invention segments the multiplexing function into multiple parallel 2:1 multiplexers operating at lower speeds (e.g., 40 Gb/s each) rather than using a single high-speed multiplexer. This allows achieving higher aggregate data rates (e.g., 160 Gb/s) by combining multiple lower-rate channels, thus resolving the contradiction between maintaining lower device complexity and achieving higher productivity.
Solution Approach 2:
The invention transitions from a single-channel high-speed approach to a multi-channel parallel architecture. By adding the dimension of parallelism with multiple independent multiplexing paths, the system achieves higher overall data transmission rates while each individual multiplexer operates at manageable speeds, resolving the contradiction between transmission rate and device complexity.
2Productivity
If higher data rates are achieved using conventional technologies, then the productivity increases, but the device complexity and cost increase significantly
Solution Approach 1:
The invention divides the high-speed multiplexing task into multiple lower-speed multiplexing operations. Each individual multiplexer operates at conventional speeds (e.g., 40 Gb/s) using established, cost-effective technologies, while the aggregate system achieves higher rates (e.g., 160 Gb/s). This segmentation allows using mature, inexpensive components rather than requiring expensive cutting-edge high-speed components.
Solution Approach 2:
The invention uses multiple copies of identical or similar lower-speed multiplexer circuits operating in parallel. Rather than designing and manufacturing a single complex high-speed multiplexer, the system replicates simpler, well-understood circuit designs, achieving high aggregate throughput through parallelism while maintaining ease of manufacture and lower cost per channel.
3Device complexity
If a single high-speed multiplexer is used, then the device complexity is reduced, but the noise increases and multiplexing efficiency decreases
Solution Approach 1:
The invention segments the high-speed multiplexing function into multiple parallel lower-speed multiplexers. Each multiplexer operates independently at lower speeds with correspondingly lower noise levels. The parallel architecture distributes the processing load and noise generation across multiple units rather than concentrating it in a single high-speed device, thus reducing overall noise while maintaining functional equivalence.
Solution Approach 2:
The invention moves from a single-dimensional high-speed approach to a multi-dimensional parallel architecture. By distributing the multiplexing function across multiple independent channels operating in parallel, the system reduces the noise and stress on any single component while achieving the same or higher aggregate throughput, effectively trading architectural complexity for reduced harmful factors.
Data Source
AI summary
The field of the invention is that of electronic or electro-optical multiplexers for the transmission of digital data at high speed. The device according to the invention makes it possible to multiplex two NRZ-type, binary-coded signals. It mainly comprises: • A generator of four primary signals; • Means of electronically selecting said primary signals controlled by the two initial signals for generating the final multiplexed signal. The selection means are complemented with a logic block for generating four logic signals, all different, dependent on the two initial signals. The main advantage of this device is to allow for the use of so-called ETDM technologies for the transmission of high-speed multiplexed signals inasmuch as the necessary logic circuits operate mainly at a frequency half that of the multiplexed signal. These electronic transmission technologies are less expensive than the so-called OTDM optical technologies.