Parallel Multiplier-Accumulator Circuit for Neural Network Convolution
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Solution Overview
Problem
Conventional neural processors relying solely on CPUs for machine learning operations face significant bandwidth consumption and increased power usage due to the extensive computing requirements of convolution operations in neural networks.
Innovation Solution
A neural processor circuit with a multiply-accumulator design that includes parallel multiplier circuits operating in both floating-point and integer modes, allowing for accelerated multiply-add operations without additional shifters, thereby reducing power consumption and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel multiplier circuits are added to accelerate convolution operations, then computational speed is improved, but device complexity increases
Solution Approach 1:
The patent implements a unified multiply-accumulate circuit that performs both multiplication and accumulation functions using shared hardware resources. The same multiplier circuit is used for both multiplying input data with kernel coefficients and accumulating the results, eliminating the need for separate multiplier and adder circuits for each operation. This multi-functional approach accelerates convolution operations while controlling device complexity.
Solution Approach 2:
The patent merges the multiplication and accumulation operations into a single integrated circuit unit. Instead of having separate multiplier circuits and adder circuits operating independently, the design combines these functions into one unified block that processes multiply-accumulate operations in a single pipeline, reducing overall circuit complexity while maintaining high computational throughput.
2Productivity
If dedicated neural processing hardware is implemented, then computational efficiency is improved, but power consumption increases
Solution Approach 1:
The neural processing circuit is designed as a universal accelerator that can handle different types of neural network operations (convolution, fully connected layers, etc.) using the same hardware resources. The multiply-accumulate circuits can be dynamically configured to perform different mathematical operations, maximizing computational efficiency while minimizing power consumption by avoiding dedicated hardware for each operation type.
Solution Approach 2:
The patent employs configurable parameters that allow the neural processing circuit to adapt its operation mode based on the specific computational task. By changing operational parameters such as precision requirements, activation functions, and data formats, the circuit optimizes its power consumption profile while maintaining high computational efficiency for different neural network workloads.
3Use of energy by moving object
If integer mode multiplication is used for neural network operations, then power consumption is reduced, but precision is limited
Solution Approach 1:
The patent implements a dynamic precision management system that adjusts the computational precision based on the specific neural network layer and operation being performed. For operations where high precision is critical (such as early layers), the system uses higher precision integer arithmetic, while for later layers where approximate computations are acceptable, it uses lower precision modes. This dynamic adaptation reduces overall power consumption while maintaining necessary precision where required.
Solution Approach 2:
The system utilizes configurable precision parameters that can be set according to the neural network architecture and application requirements. By changing the bit-width and precision parameters of the integer arithmetic operations, the patent enables a trade-off between power consumption and computational precision, allowing optimization for specific use cases such as mobile devices or edge computing applications.
Data Source
AI summary
Embodiments of the present disclosure relate to a multiply-accumulator circuit that includes a main multiplier circuit operable in a floating-point mode or an integer mode and a supplemental multiplier circuit that operates in the integer mode. The main multiplier circuit generates a multiplied output that undergoes subsequent operations including a shifting operation in the floating-point mode whereas the supplemental multiplier generates another multiplied output that does not undergo any shifting operations. Hence, in the integer mode, two parallel multiply-add operations may be performed by the two multiplier circuits, and therefore accelerate the multiply-adder operations. Due to the lack of additional shifters associated with the supplemental multiplier circuit, the multiply-accumulator circuit does not have a significantly increased footprint.