Parallel Multiplier Circuit for Low-Latency Long Integer Multiplication
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Solution Overview
Problem
Current methods for multiplying very long integers, such as those used in encryption and blockchain technologies, are time-consuming due to the need to compute and sum multiple intermediate products sequentially, leading to significant latency in the process.
Innovation Solution
A computer-implemented method and system that uses a multiplier circuit to calculate partial products and reduce them into intermediate results with sum and carry values, which are then combined and added in a reduction tree to produce a final result, allowing for the reduction of latency by processing multiple products in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple intermediate products are computed and summed sequentially using traditional methods, then the multiplication of very long integers can be completed, but the process becomes time-consuming and latency increases
Solution Approach 1:
The patent segments the multiplication process into parallel stages: multiple multiplier circuits simultaneously compute different intermediate products (A×D, B×C, etc.), and multiple adders simultaneously sum these products. This segmentation of the computational process into independent parallel operations resolves the contradiction by maintaining accuracy through complete computation while dramatically reducing latency through simultaneous execution of multiple segments.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to two-dimensional parallel processing by organizing multiple multiplier circuits and adder circuits in a matrix-like structure. The intermediate products are arranged in rows and columns, with horizontal adders summing rows and vertical adders summing columns, creating a dimensional expansion that enables simultaneous computation and reduces overall computation time while maintaining mathematical accuracy.
2Productivity
If a reduction circuit reduces partial products to create intermediate results with sum and carry values, then the number of operations is reduced, but the circuit complexity increases
Solution Approach 1:
The reduction circuit is segmented into specialized sub-circuits: horizontal adders for row-wise summation, vertical adders for column-wise summation, and a final carry propagation circuit. Each segment performs a specific function with optimized logic, reducing the overall complexity compared to a monolithic reduction circuit while improving productivity through parallel operation of these segmented components.
Solution Approach 2:
The reduction circuit employs dynamic carry propagation where carry bits are generated and propagated through multiple stages in a controlled sequence. The circuit dynamically adjusts the propagation of carry values through the partial products, enabling faster reduction than static methods while managing complexity through staged, controlled carry handling rather than exhaustive simultaneous computation.
Data Source
AI summary
Methods, systems and computer program products for computing and summing up multiple products in a single multiplier are provided. Aspects include receiving a first number and a second number, creating partial products of the first number and the second number based on a multiplication of the first number and the second number, and reducing the number of partial products to create an intermediate result. Aspects also include receiving a third number and a fourth number, creating partial products of the third number and the fourth number based on a multiplication of the third number and the fourth number, creating a reduction tree and adding the intermediate result to the reduction tree. Aspects further include reducing the number of partial products in the reduction tree to create a second sum value and a second carry value and adding the second sum value and the second carry value to create a result.