Parallel Multiplier Execution Unit for Neural Network Math
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Solution Overview
Problem
Existing execution units for processors face challenges in quickly and accurately generating values for mathematical functions like divide, exponential, logarithm, and square root, particularly in neural network processing, where resource optimization is crucial.
Innovation Solution
An execution unit with a processing pipeline comprising multiple stages and multiplier circuits, where first and second multiplier circuits operate in parallel, and a third multiplier processes their outputs in series, along with additional processing circuitry for operations like addition and subtraction, enables efficient evaluation of various mathematical functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single multiplier circuit is used in the execution unit, then the device complexity is reduced, but the processing speed and productivity for evaluating mathematical functions deteriorates
Solution Approach 1:
The execution unit is divided into multiple multiplier circuits (first multiplier, second multiplier, third multiplier) that operate in parallel to evaluate different parts of mathematical functions simultaneously. This segmentation allows the processing pipeline to handle multiple operations concurrently, improving productivity without significantly increasing overall device complexity through modular design.
Solution Approach 2:
The patent introduces a time dimension through pipelined processing, where multiple multiplier circuits operate at different stages of the pipeline. The first and second multipliers work in parallel at one stage, while the third multiplier processes their outputs in a subsequent stage, effectively adding temporal dimensionality to the processing architecture to enhance throughput.
2Speed
If multiple multiplier circuits operate in parallel, then the processing speed improves, but the device complexity increases
Solution Approach 1:
Multiple multiplier circuits are merged into a unified processing pipeline with shared control logic and data paths. The first, second, and third multipliers are integrated through a common pipeline structure that coordinates their parallel operation, reducing the overall complexity compared to having separate independent multiplier units.
Solution Approach 2:
The multiplier circuits are designed to perform multiple mathematical functions (divide, exponential, logarithm, square root) through a universal processing pipeline. By making the multiplier circuits multi-functional rather than dedicated to single operations, the patent reduces the need for separate specialized circuits for each function, thereby managing device complexity while maintaining high processing speed.
3Productivity
If a processing pipeline with multiple stages is implemented, then the productivity for evaluating multiple mathematical functions improves, but the device complexity increases
Solution Approach 1:
The processing pipeline is segmented into distinct stages, each handled by specific multiplier circuits. The first multiplier handles initial calculations, the second multiplier processes intermediate results in parallel, and the third multiplier finalizes the computation. This segmentation enables high throughput by allowing different stages to progress simultaneously through the pipeline.
Solution Approach 2:
The pipeline architecture performs preliminary actions in early stages (first and second multipliers) so that subsequent stages (third multiplier) can process results without waiting for complete computation. This preliminary processing in parallel stages prepares data in advance, improving overall productivity while managing complexity through staged preparation.
Data Source
AI summary
An execution unit comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions. The processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result. Each of a plurality of processing circuits in the pipeline is configured to perform an operation on input values during at least one stage of the plurality of stages. The plurality of processing circuits include multiplier circuits. A first multiplier circuit and a second multiplier circuit are configured to operate in parallel, such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform their processing. A third multiplier circuit is arranged in series with the first multiplier circuit and the second multiplier circuit and processes outputs from the first multiplier circuit and the second multiplier circuit.