Parallel Mux Delay Interpolator for Fine Resolution Timing
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Solution Overview
Problem
Existing digital delay interpolators require multiple stages in cascade to achieve high delay resolution, leading to increased propagation delays and power consumption.
Innovation Solution
A digital delay interpolator using 2×1 multiplexers connected in parallel, eliminating the need for inverters and allowing for any phase mixing resolution with a single stage, and optionally combining stages in a mixed series-parallel architecture for enhanced resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay stages are connected in cascade to achieve high delay resolution, then the delay resolution is improved, but the propagation delay and power consumption increase
Solution Approach 1:
The delay interpolation function is segmented across multiple parallel multiplexer units rather than sequential stages. Each multiplexer handles a portion of the delay resolution requirement, allowing simultaneous operation that achieves fine delay resolution without cascading delays.
Solution Approach 2:
The architecture transitions from a sequential one-dimensional stage cascade to a parallel multi-dimensional multiplexer array. This dimensional change enables achieving the same delay resolution through parallel spatial distribution rather than sequential temporal processing, eliminating the propagation delay accumulation.
2Measurement precision
If multiple delay stages are connected in cascade to achieve high delay resolution, then the delay resolution is improved, but the power consumption increases
Solution Approach 1:
The power consumption burden is segmented and distributed across multiple parallel multiplexer units operating simultaneously at lower individual power levels, rather than concentrating high power requirements in sequential stages. This parallel segmentation reduces total power consumption while achieving the same delay resolution.
Solution Approach 2:
Multiple multiplexer units are merged into a single parallel architecture that achieves delay resolution through coordinated simultaneous operation. This merging eliminates the need for multiple sequential stage operations, reducing cumulative power consumption while maintaining high delay resolution.
3Measurement precision
If the number of stages in cascade is increased to enhance accuracy, then the delay accuracy is improved, but the device complexity increases
Solution Approach 1:
The multiplexer units are designed as universal building blocks that perform multiple functions: delay selection, phase interpolation, and signal routing. This multi-functionality eliminates the need for separate dedicated circuits for each function, reducing overall device complexity while achieving high delay accuracy.
Solution Approach 2:
The architecture uses homogeneous multiplexer units repeated in parallel rather than heterogeneous sequential stages. This homogeneity simplifies design, fabrication, and testing by using identical standardized cells, reducing device complexity while achieving high accuracy through parallel coordination.
Data Source
AI summary
A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.