Parallel NOR Decoder Architecture for Large Single-Stage Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NOR decoders are limited by physical restrictions that restrict the number of inputs to a single decode unit, often requiring multiple stages of decoding for structures with large numbers of inputs, leading to increased setup times and decreased clock performance.
Innovation Solution
A NOR decoder design that integrates multiple decode circuits onto different nodes and combines them in a single stage using an additional NFET and PFET in the evaluation circuit, allowing more than four inputs to be decoded concurrently without the need for pre-decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple stages of decoding are used for large numbers of inputs, then the physical limitation of inputs per decode unit is satisfied, but the setup time increases and clock performance decreases
Solution Approach 1:
The patent divides the decode inputs into multiple groups (first set and second set of inputs) that are processed by separate NOR decode circuits operating in parallel. This segmentation allows the decoder to handle more inputs than a single circuit could manage while maintaining single-stage operation, thereby reducing setup time compared to multi-stage approaches.
Solution Approach 2:
The patent merges multiple NOR decode circuits into a single decode stage where their outputs are combined through an evaluation circuit. This combining approach enables the system to process large numbers of inputs concurrently in one stage rather than requiring sequential multi-stage decoding, thus improving clock performance while handling large input counts.
2Adaptability or versatility
If multiple stages of decoding are used, then large numbers of inputs can be handled, but the device complexity and space requirements increase
Solution Approach 1:
The patent segments the input signals into multiple sets that are fed to parallel NOR decode circuits. This segmentation strategy allows the system to scale to handle large numbers of inputs (6-to-64, 9-to-512, 12-to-4096 schemes) by adding parallel circuits rather than adding sequential stages, thereby reducing device complexity.
Solution Approach 2:
Instead of increasing decode capacity by adding temporal stages (time dimension), the patent transitions to a spatial solution by adding parallel NOR decode circuits operating simultaneously. This dimensional shift from sequential to parallel architecture reduces device complexity while maintaining the ability to handle large input numbers.
3Loss of time
If more inputs are decoded in a single stage, then setup time is reduced, but the physical limitations of decode units are exceeded
Solution Approach 1:
The patent segments the large input set into smaller manageable groups (first set and second set), each processed by a dedicated NOR decode circuit. This segmentation enables single-stage operation with reduced delay while respecting the physical input limitations of individual decode units, as each unit handles only its assigned subset of inputs.
Solution Approach 2:
The patent merges the outputs of multiple parallel NOR decode circuits through an evaluation circuit to produce the final decode result. This merging approach allows the system to effectively handle more inputs than any single circuit could manage alone, achieving high input capacity in a single stage without exceeding individual unit limitations.
Data Source
AI summary
A NOR decoder for large decode structures includes a first NOR decode circuit connected by a first node to an evaluation circuit. The first NOR decode circuit is configured to receive a first set of three or more inputs. The evaluation circuit is connected to a second node. The NOR decoder also includes a second NOR decode circuit connected by a third node to the evaluation circuit. The second NOR decode circuit is configured to receive a second set of three or more inputs. The evaluation circuit is configured to change a state of the second node in response to an active clock signal and all inputs in the first set and the second set having the same logical value.