Parallel NTT Accelerator for Homomorphic Ciphertext Multiplication
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Solution Overview
Problem
Existing homomorphic encryption systems face inefficiencies in computational speed due to the large size of homomorphic ciphertexts, particularly in multiplication operations, and existing hardware structures are not practical for handling these operations effectively.
Innovation Solution
A parallel computational structure is implemented using a number theoretic transform (NTT) algorithm with a single-path delay feedback (SDF) scheme, arranging processing elements in parallel to perform polynomial operations, and optimizing twiddle factor storage to improve computational speed without increasing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a hardware operator based on number theoretic transform (NTT) is used to improve computational speed, then the speed of homomorphic ciphertext computation is improved, but the hardware complexity and storage requirements increase significantly due to the large size of homomorphic ciphertexts
Solution Approach 1:
The patent divides the homomorphic encryption computation into multiple parallel processing elements, each handling a portion of the polynomial coefficients. This segmentation allows the large-scale NTT operation to be distributed across multiple units, reducing the computational burden on each individual unit while maintaining overall high-speed computation.
Solution Approach 2:
The patent transitions from a single-path sequential processing architecture to a multi-path parallel architecture by introducing multiple processing elements that operate simultaneously on different data streams. This dimensional change from 1D sequential to 2D parallel processing enables significant speedup while managing hardware complexity through structured organization.
2Device complexity
If the size of homomorphic ciphertext is reduced to simplify hardware structure, then the hardware complexity is reduced, but the computational precision and encryption security are compromised
Solution Approach 1:
The patent applies different processing strategies to different parts of the ciphertext data. Each processing element is optimized for its specific portion of the polynomial coefficients, with specialized logic for handling local computational requirements while maintaining global consistency and precision through coordinated operation.
Solution Approach 2:
The patent optimizes computational parameters such as the modulus values and polynomial degree distribution across processing elements to achieve the right balance between hardware complexity and computational precision. By carefully selecting and adjusting these parameters, the system maintains encryption security and computation accuracy while enabling practical hardware implementation.
Data Source
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AI summary
Disclosed is a homomorphic encryption calculating accelerator which includes a parallel processing unit performing a polynomial multiplication operation in parallel on a plurality of input data corresponding to a degree N polynomial of a homomorphic ciphertext and a combination unit generating a plurality of output data by performing the polynomial multiplication operation on an output of the parallel processing unit. The parallel processing unit includes a first parallel processing element performing the polynomial multiplication operation on first input data among the plurality of input data and a second parallel processing element performing the polynomial multiplication operation on second input data among the plurality of input data. The first parallel processing element and the second parallel processing element are arranged in parallel, and each of the first parallel processing element and the second parallel processing element has a single-path delay feedback (SDF) number theoretic transform (NTT) hardware structure.