Parallel NTT/INTT Butterfly Circuit for Low-Latency Polynomial Multiplication
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Solution Overview
Problem
The advent of quantum computers poses a significant threat to the security of existing public-key cryptosystems, such as RSA and ECC, as they can be potentially broken using Shor's algorithm, necessitating a transition to post-quantum cryptosystems like lattice-based cryptosystems to ensure long-term security in cloud computing.
Innovation Solution
Implementing a circuit architecture that utilizes multi-level parallelism and butterfly operator circuits, including Cooley-Tukey and Gentleman-Sande configurations, to perform efficient number theoretic transform (NTT) and inverse NTT (INTT) operations, reducing computational complexity from O(n^2) to O(n log n) and accelerating polynomial multiplication in lattice-based cryptosystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential algorithms are used for NTT/INTT, then implementation simplicity is maintained, but computational complexity is O(n^2) and processing time is excessive
Solution Approach 1:
The NTT/INTT computation is divided into multiple stages, with each stage processing a subset of coefficients. The circuit is segmented into parallel butterfly operator circuits that each handle specific coefficient pairs, allowing the overall computation to be broken down into manageable parallel tasks that reduce complexity from O(n^2) to O(n log n).
Solution Approach 2:
The patent transitions from sequential single-threaded computation to multi-dimensional parallel processing by implementing multiple butterfly operator circuits operating simultaneously at different stages. This dimensional expansion into parallel computation paths enables significant speedup while managing complexity through structured organization of the parallel elements.
2Loss of time
If multi-level parallelism is implemented to reduce computational complexity to O(n log n), then processing speed increases, but circuit complexity and resource requirements increase
Solution Approach 1:
Multiple butterfly operator circuits are merged into a unified hierarchical structure where stages are combined efficiently. The patent merges parallel processing paths by organizing butterfly circuits in series-parallel configurations, allowing time latency to be reduced while sharing common resources and minimizing redundant circuitry across the parallel stages.
Solution Approach 2:
The circuit architecture employs dynamic resource allocation where butterfly operator circuits are activated in different stages based on computation requirements. The parallel circuits can be dynamically configured to process different coefficient pairs at different clock cycles, optimizing resource utilization and reducing the effective number of circuits needed at any given moment.
3Productivity
If parallel butterfly operator circuits are used, then NTT/INTT throughput increases to 1,602 k operations/second, but memory access overhead increases
Solution Approach 1:
Input coefficients are pre-organized and loaded into register files before the parallel butterfly operator circuits begin processing. This preliminary action ensures that all necessary data is available in fast memory at the start of computation, minimizing the need for repeated memory accesses during the parallel processing stages and reducing overall memory access overhead.
Solution Approach 2:
The parallel butterfly operator circuits are designed to operate continuously without idle cycles, with each circuit processing coefficients in an uninterrupted sequence. This continuous operation maximizes throughput by keeping all computational resources actively engaged, reducing the total computation time and thereby reducing the cumulative memory access overhead across all parallel operations.
Data Source
AI summary
Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT)/inverse NTT (INTT). A circuit for NTT/INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.