Parallel NVDIMM Architecture with Interface Bridge Chips
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Solution Overview
Problem
Existing memory module designs face challenges with high latency in accessing storage devices, signal interference, and limited performance due to the use of a single FPGA chip for data transfer between DRAM and NAND Flash chips, which results in wire clogging and increased costs.
Innovation Solution
A parallel NVDIMM architecture utilizing multiple interface bridge chips as processors to facilitate parallel data transfer between DRAM and non-volatile memory devices, allowing for a dispersed and efficient layout design without signal integrity issues and reducing the need for extensive I/O pins on the FPGA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single FPGA chip is used to facilitate data transfer between DRAM and NAND Flash chips, then the layout design becomes constrained and wire clogging occurs, but using multiple interface bridge chips enables dispersed layout and reduces wire congestion
Solution Approach 1:
The patent divides the single FPGA chip into multiple interface bridge chips, each handling a portion of the data transfer task. This segmentation allows the components to be dispersed across the PCB, reducing wire congestion and simplifying layout design while maintaining the overall data transfer functionality.
Solution Approach 2:
The patent transitions from a single-point concentration of data transfer operations to a distributed spatial arrangement across multiple chips. This dimensional shift from centralized to distributed architecture resolves the wire clogging issue by spreading connections across multiple locations on the PCB.
2Device complexity
If a single FPGA chip is used for data transfer, then the I/O pin requirement increases significantly, but using multiple interface bridge chips distributes the I/O requirements
Solution Approach 1:
The patent segments the I/O pin requirements across multiple interface bridge chips instead of concentrating them on a single FPGA chip. Each chip handles a subset of data transfer operations, reducing the I/O pin count requirement for each individual chip and thereby reducing overall manufacturing cost.
3Productivity
If a single processor is used to handle data transfer between DRAM and NAND Flash, then the performance is limited by sequential processing, but using multiple processors enables parallel data transfer and improves performance
Solution Approach 1:
The patent segments the data transfer function across multiple interface bridge chips, each capable of independent data transfer operations. This segmentation enables parallel processing of data transfer tasks, significantly improving productivity while the modular nature of the chips keeps the complexity increase manageable.
Solution Approach 2:
The patent enables continuous data transfer operations through multiple parallel processors that can simultaneously handle different data transfer tasks. This eliminates the sequential bottlenecks of a single processor, maintaining continuous productive action throughout the data transfer process.
4Reliability
If all data bits are routed to a single FPGA chip location, then the data transfer function is achieved, but severe wire clogging and signal interference occur
Solution Approach 1:
The patent segments the data routing function across multiple interface bridge chips distributed on the PCB. This segmentation eliminates the need for all data bits to converge at a single location, thereby reducing wire routing complexity and improving signal integrity by shortening individual trace lengths and reducing congestion.
Data Source
AI summary
A non-volatile memory module in parallel architecture is described. It includes memory function and data storage function in a single module. It enables host system to use memory bus to access storage devices and to use the same memory command protocol for storage device access. The parallel architecture enables contents in memory devices and storage devices to be exchanged freely on module under the control of host memory controller to boost performance of computer and to retain data even if power to computer is shut off. The configuration of non-volatile memory module can be partitioned or expanded into multiple independent channels on module seamlessly with or without ECC supports.