Parallel Object Detection on Heterogeneous Microarchitectures
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Solution Overview
Problem
Current object detection methods in images for heterogeneous multithreaded microarchitectures, such as those combining CPUs and GPUs, fail to fully exploit the computing capabilities for efficient processing of high-resolution images and video frames, leading to high latency in object detection.
Innovation Solution
A parallel object detection method that utilizes multiple levels of parallelism by generating downscaled images and executing data-parallel kernel operations, including computation of summed area tables through decomposition into data-parallel prefix sum and parallel transposition operations, and concurrent scheduling of kernel operations across multiple cores and SIMD processing units to maximize occupancy and memory bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the amount of arithmetic and logic units (ALUs) within each CPU core is increased to reduce object detection latency, then the processing speed improves, but the chip die area spent on caches, buffers and speculation logic increases, reducing the available area for additional functional units
Solution Approach 1:
The patent segments the object detection workload across multiple CPU cores and GPU streaming processors, dividing the image processing tasks into parallel workloads. This allows the system to achieve high processing speed without concentrating all ALUs in a single core, thus avoiding the need for proportionally larger cache and buffer structures in one location.
Solution Approach 2:
The patent transitions from a single-core CPU architecture to a heterogeneous multi-core CPU-GPU architecture, adding spatial dimensions of parallelism. By distributing processing across multiple cores and streaming processors, the system achieves high throughput without requiring excessive die area in any single location, as memory structures are shared across the heterogeneous architecture.
2Productivity
If data-parallel kernel operations are executed across multiple cores and SIMD processing units to maximize occupancy, then the processing throughput improves, but the complexity of memory access patterns and synchronization increases
Solution Approach 1:
The patent employs local memory (shared memory) within each GPU streaming processor cluster to store frequently accessed image data and intermediate results. This local quality approach allows each processing unit to access its local data with high bandwidth without interfering with other clusters, simplifying the overall memory access pattern while maintaining high throughput through data locality.
Solution Approach 2:
The patent implements continuous data flow through the pipeline by pre-loading image data into shared memory before processing and maintaining steady streams of data between processing stages. This continuity eliminates idle cycles and reduces the need for complex synchronization mechanisms, as data flows continuously through the parallel processing units without gaps or conflicts.
3Measurement precision
If the boosted cascade of classifiers is evaluated sequentially to maintain detection accuracy, then the measurement precision improves, but the processing time increases
Solution Approach 1:
The patent segments the image processing workload by dividing the image into multiple regions of interest (ROIs) and assigning different ROI processing to different GPU streaming processors. Within each ROI, the cascade classifier is evaluated sequentially to maintain accuracy, but different ROIs are processed in parallel, effectively reducing overall processing time while preserving detection precision through segmented parallelism.
Solution Approach 2:
The patent performs preliminary downscaling of the input image to multiple resolution levels before classification. This preliminary action reduces the computational burden of the cascade classifier by processing a downsampled version first, allowing rapid filtering of obvious non-objects, while maintaining full-resolution accuracy only for regions that require detailed examination, thus reducing overall processing time without sacrificing precision.
Data Source
AI summary
A parallel object detection method for heterogeneous microarchitectures. The method is designed for increasing the throughput of object detection in a computer system that is equipped with an array of cores including a shared memory, a constant memory, and functional units. Latency reduction is achieved through a multilevel parallelization method that exploits fine-grain data-level parallelism using multithreaded SIMD computations, and coarse-grain parallelism by relying on concurrent kernel execution.