Parallel OTPM Programming Reduces Test Time

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

One-time programmable memory (OTPM) systems require extensive test time due to sequential programming and lack of pre-shipping verification of wordline decoders, leading to inefficiencies and potential Time Dependent Dielectric Breakdown (TDDB) failures.

Innovation Solution

Implementing parallel programming across all banks of the OTPM by writing and verifying two rows per bank simultaneously, using sacrificial input/output logic and local overwrite protection to reduce test time and prevent TDDB, while enabling testing of wordline decoders before shipping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If sequential programming is used in OTPM systems, then programming accuracy is maintained, but test time becomes excessively long (65 seconds for full memory)

Engineering Contradiction:
Improvetest timeVSAvoidprogramming speed
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent segments the memory array into multiple banks and further divides each bank into rows that can be programmed independently and in parallel. By organizing the memory structure into separable units (banks, rows, columns) that can be addressed simultaneously, the system achieves parallel programming while maintaining verification accuracy through dedicated sense amplifiers for each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces parallelism across multiple dimensions simultaneously - multiple banks are programmed in parallel, and within each bank, multiple rows are programmed in parallel. This multi-dimensional parallel approach transforms the sequential single-dimension programming into a concurrent multi-dimensional operation, reducing total test time from 65 seconds to 4 seconds.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If extensive testing is performed on wordline decoders before shipping, then reliability is improved, but test time increases significantly

Engineering Contradiction:
Improvewordline decoder verificationVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary verification of wordline decoders and memory functionality during the programming process itself, before the product is shipped. By integrating verification operations into the programming flow and using parallel execution, the system validates decoder functionality in advance, eliminating the need for separate extensive post-manufacturing testing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous useful action by performing verification operations concurrently with programming operations. Instead of sequential verify-then-program or program-then-verify approaches, the system continuously performs both operations in parallel, ensuring decoder reliability is verified without interrupting the programming flow or adding significant time overhead.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If parallel programming of multiple rows is implemented, then programming speed is improved, but risk of time dependent dielectric breakdown increases

Engineering Contradiction:
Improveprogramming speedVSAvoidtime dependent dielectric breakdown
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent rushes through the programming process by completing multiple row programming operations in parallel before verification, rather than verifying each row sequentially after programming. This approach minimizes the total time rows remain in a vulnerable intermediate state, reducing exposure to time dependent dielectric breakdown while maintaining high programming speed through parallel execution.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS10062445B2Parallel programming of one time programmable memory array for reduced test time
Publication Date: 2018.08.28 GLOBALFOUNDRIES US INC
  • US10062445B2 patent drawing
  • US10062445B2 patent drawing
  • US10062445B2 patent drawing

AI summary

The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank.