Parallel Output Buffer Circuit for Variable Drive Strength
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Solution Overview
Problem
Existing output buffer circuits are either on or off, leading to a 'one size fits all' design that fails to customize drive strength according to specific purposes and coupled circuits, complicating the design and potentially resulting in unsuitable driver capability for different applications.
Innovation Solution
A plurality of output buffer circuits are coupled in parallel to provide a combined output drive strength, with each circuit receiving shared and customized enable signals to adjust the drive strength, allowing for logically high, low, or floating output values, ensuring suitable driver capability for varying applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single output buffer circuit is used with fixed drive strength, then device complexity is reduced, but adaptability to different application requirements deteriorates
Solution Approach 1:
The output buffer circuit is divided into multiple parallel buffer circuits (first output buffer circuit, second output buffer circuit, etc.), each with its own enable signal. This segmentation allows individual buffers to be selectively activated, providing variable drive strength without requiring completely different circuit designs for each application.
Solution Approach 2:
The patent introduces dynamic control through enable signals (first enable signal, second enable signal, etc.) that can selectively activate or deactivate individual buffer circuits. This dynamic control allows the system to adapt its drive strength in real-time based on application requirements, transforming a static fixed-drive-strength system into a dynamic variable-drive-strength system.
2Adaptability or versatility
If multiple output buffer circuits with customized drive strength are used, then adaptability to different applications is improved, but device complexity increases
Solution Approach 1:
Multiple buffer circuits are designed with identical structures and functionalities, each capable of operating independently. This universal design allows the same buffer circuit blueprint to be replicated multiple times, providing drive strength customization without proportionally increasing design complexity. Each buffer serves multiple purposes depending on which enable signals are active.
Solution Approach 2:
Multiple parallel buffer circuits are merged into a single output node, where their outputs are combined. This merging allows the system to achieve variable drive strength by selectively enabling individual buffers, while sharing common resources such as the output node and control logic, thereby limiting the increase in overall device complexity.
3Power
If all output buffer circuits are enabled, then output drive strength is maximized, but power consumption increases
Solution Approach 1:
Instead of always enabling all buffer circuits (excessive action), the system enables only the necessary number of buffers required to achieve the desired drive strength (partial action). The enable signals allow selective activation, so the system uses just enough power to meet the current application's drive strength requirements without wasting energy on unnecessary buffers.
Solution Approach 2:
The enable signals provide dynamic control over buffer activation, allowing the system to adjust power consumption in real-time based on the required output drive strength. When high drive strength is needed, more buffers are enabled; when lower drive strength suffices, fewer buffers are active, thereby reducing power consumption dynamically matched to actual needs.
Data Source
AI summary
An output buffer circuit has a variable output drive strength, depending on a buffer enable signal. Multiple output buffer circuits have a variable combined output drive strength, depending on a set of buffer enable signals.