Parallel Packet Processing Order Maintenance via Dynamic Queue Feedback
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Solution Overview
Problem
Network devices face challenges in maintaining the order of packets during parallel processing due to variability in latency among processing elements, leading to out-of-order completion of packet processing.
Innovation Solution
A controller device with an instruction execution processor and memory that manages queues for packet identifiers, using feedback processors to ensure packets are processed and transmitted in the correct order by identifying and executing instructions only when packets reach the head of their respective queues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel packet processing is implemented to improve throughput, then productivity increases, but packet order maintenance becomes difficult leading to out-of-order completion
Solution Approach 1:
The system segments packets into different queues based on their processing requirements and latency characteristics. By dividing the packet stream into multiple ordered queues, each queue can be processed independently while maintaining overall packet order, thus enabling parallel processing without losing packet sequence integrity.
Solution Approach 2:
The system performs preliminary actions by pre-classifying packets into different queues before processing based on their latency requirements. This advance organization allows the packet ordering processor to efficiently retrieve and process packets in the correct order without requiring complex real-time reordering operations.
2Speed
If multiple processing elements are used to process packets concurrently, then processing speed increases, but variability in latency causes packets to complete out of order
Solution Approach 1:
The system applies local quality by assigning different service priorities and latency treatments to different queues based on their specific requirements. High-latency packets are placed in queues with relaxed timing, while low-latency packets receive priority processing, ensuring each packet type is handled with appropriate quality of service while maintaining overall order.
Solution Approach 2:
The packet ordering processor acts as an intermediary between the parallel processing elements and the output interface. It receives packets from multiple processing elements, reorders them according to their original sequence, and then forwards them in the correct order, thus mediating the conflict between parallel processing speed and order precision.
3Reliability
If packets are buffered to maintain order, then packet order is preserved, but processing delay increases
Solution Approach 1:
The system uses dynamic queue management where the buffering behavior adapts based on current queue states and packet characteristics. Rather than using a single static buffer, multiple dynamic queues allow packets to be held in different buffering states, enabling the system to maintain order while minimizing unnecessary delays by releasing packets as soon as they are ready in the correct sequence.
Data Source
AI summary
An instruction execution processor has an input to receive instructions associated with maintaining a queue for storing packet identifiers (IDs) corresponding to packets being processed by a network device. A memory coupled to the instruction execution processor is for storing instructions received at the input of the instruction execution processor and not executed by the instruction execution processor. An instruction feedback processor is coupled to the instruction execution processor. The instruction feedback processor is configured to, in response to receiving an output from the instruction execution processor, identify one or more instructions, stored in the memory, that correspond to a new packet ID at the head of the queue, and feed back, to the input of the instruction execution processor, the one or more identified instructions.