Parallel Packet Processing Pipeline for Multi-Core Systems
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Solution Overview
Problem
Existing high-performance computing solutions, such as ASICs and network processors, are expensive to develop and lack flexibility, leading to limited scalability and slow evolution in network functionality due to their hard-coded nature and high costs.
Innovation Solution
A parallel-processing computer system that uses a single pipeline to process data packets, allowing multiple processing elements to execute tasks in parallel, reducing software queues and memory transactions, and enabling native service chaining without packet copying or software locks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASICs are used for high-performance computing, then processing speed and throughput are improved, but development cost and device complexity increase significantly
Solution Approach 1:
The system segments processing tasks into multiple sub-pipelines that can be executed in parallel by different processing elements. Each sub-pipeline handles a specific portion of the overall processing task, allowing the system to achieve high throughput without requiring a single complex ASIC. This divides the complex processing function into manageable, parallelizable units.
Solution Approach 2:
The patent employs universal processing elements that can execute multiple types of processing tasks through software configuration rather than hard-coded functions. These processing elements can be dynamically programmed to perform different operations, providing both high performance and flexibility without requiring dedicated ASICs for each function.
2Productivity
If ASICs are used for high-performance computing, then processing performance is improved, but flexibility and adaptability deteriorate due to hard-coded functions
Solution Approach 1:
The system implements dynamic processing where processing elements can be reconfigured at runtime through software to adapt to different processing requirements. The pipeline structure allows dynamic addition, removal, or modification of processing stages without hardware changes, enabling the system to adapt to new protocols, formats, or processing demands while maintaining high performance.
Solution Approach 2:
The patent utilizes parameter-based configuration where processing behavior is controlled by software parameters rather than hard-coded logic. Processing elements can change their operational characteristics through parameter adjustment, allowing the same hardware to perform multiple functions with different performance characteristics as needed.
3Reliability
If traditional software queues are used for packet processing, then processing order is maintained, but processing time and productivity decrease due to sequential handling
Solution Approach 1:
The patent segments the packet processing pipeline into multiple independent sub-pipelines that can operate in parallel. Each sub-pipeline processes a portion of the data stream simultaneously, maintaining internal order within each pipeline while achieving overall faster throughput through parallel execution rather than sequential processing.
Solution Approach 2:
The system implements continuous processing where multiple packets can be processed at different stages of the pipeline simultaneously. While one packet is being processed in early stages, other packets can advance to later stages, eliminating idle time and maintaining continuous useful action throughout the processing system.
4Reliability
If packets are copied and replaced in memory for processing, then data integrity is maintained, but memory transactions and processing overhead increase
Solution Approach 1:
The patent implements a copyless processing model where the same packet data structure can be accessed and processed by multiple processing elements simultaneously without creating copies. Memory management mechanisms ensure data integrity through proper synchronization and reference counting, eliminating the need for repeated copying while maintaining reliability.
Solution Approach 2:
The system merges multiple processing operations that would traditionally require separate memory accesses into a single unified processing pass. By combining multiple processing functions into integrated pipeline stages, the system reduces the total number of memory transactions required while maintaining data integrity through coordinated processing.
Data Source
AI summary
A parallel-processing computer system is provided for parallel processing of data packets conveyed in a communication network. The system comprises: a memory; a plurality of processing elements; and a program stored at the memory for execution by the plurality of processing elements. The at least one program comprises instructions for: receiving one or more data packets comprising operational instructions from an application; establishing a pipeline element for carrying out a service process, which comprises a plurality of sub-pipelines, each associated with a respective task required for carrying out the service process and wherein each of the plurality of processing elements is operative for carrying out tasks associated with a respective sub-pipeline belonging to the plurality of sub-pipelines; and executing simultaneously by the plurality of processing elements, tasks associated with the plurality of sub-pipelines, wherein the plurality of processing elements is implementing a parallel processing of each data packet.