Parallel PAM Coding With Voltage Permutations for Low-Pin Chip Links
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Solution Overview
Problem
Existing PAM-based coding schemes for chip-to-chip communications prioritize high-speed data transfer but often compromise on power consumption, IC footprint, and I/O pin count, failing to achieve a balanced solution for these factors.
Innovation Solution
The development of N-bit, M-wire PAM-Q coding schemes that encode data using permutations of a limited set of voltage signals across multiple wires, allowing for high-speed communication while optimizing for low power consumption and reduced pin count, with specific implementations like 4-bit, 4-wire PAM4 and 4-bit, 5-wire PAM3 schemes that utilize specific voltage level configurations to achieve efficient decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PAM-based coding schemes are designed for high-speed communication, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by utilizing PAM-Q modulation with Q voltage levels to encode multiple bits per symbol. By changing the voltage level parameters and using permutations of voltage signals, the system achieves high-speed communication while optimizing power consumption through efficient voltage utilization and reduced switching activity.
Solution Approach 2:
The coding scheme segments data into N-bit groups that are encoded using M-wire PAM-Q signaling. This segmentation allows parallel transmission of multiple bits simultaneously across multiple wires, improving speed while the structured encoding reduces overall power consumption by efficiently managing voltage transitions across the segmented data groups.
2Speed
If PAM-based coding schemes are designed for high-speed communication, then data transmission speed is improved, but IC footprint increases
Solution Approach 1:
The patent employs universal encoding patterns where permutations of a limited set of voltage signals are used across multiple wires. This multi-functional approach allows the same voltage signal set to serve multiple encoding purposes, reducing the need for additional dedicated circuitry and minimizing IC footprint while maintaining high-speed communication capabilities.
3Speed
If PAM-based coding schemes are designed for high-speed communication, then data transmission speed is improved, but I/O pin count increases
Solution Approach 1:
The patent transitions from traditional single-wire serial communication to multi-wire parallel communication with PAM-Q modulation. By adding the spatial dimension of multiple wires and utilizing voltage level dimensionality (Q levels), the system achieves high-speed data transmission while efficiently utilizing the available I/O pins through parallelism rather than requiring proportionally more pins for speed increases.
4Speed
If complex decoding processes are used to achieve high-speed communication, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-defining permutation patterns for voltage signals during the encoding phase. The encoder prepares and transmits signals according to predetermined permutation rules, which allows the decoder to use simpler lookup or comparison-based decoding logic rather than complex real-time computation, thus achieving high-speed communication with reduced decoding complexity.
Data Source
AI summary
Encoders and decoders for encoding and decoding data according to a coding scheme. The encoder converts N bits of input data into M voltage signals for transmission over M parallel wires to a decoder having one or two decoding stages that recover the N bits of data from the M voltage signals. The coding scheme is an N-bit, M-wire PAM-Q code in which each voltage signal wi has one of Q voltage levels l1-lQ, where l1<l2< . . . <lQ, and the different sets of M voltage signals for the different N-bit input values are permutations of a single set of M voltage signals. The decoder has a comparator stage. For the decoder having one other decoding stage, the other decoding stage is a computation stage or a logic stage that is before or after the comparator stage.