Parallel Parity Processing Circuits for Line-Rate Data Frames
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Solution Overview
Problem
Existing circuit technologies face challenges in achieving high throughput and low latency for generating and checking parity bits in communication and mass storage systems, particularly in serial implementations that cannot operate at line rates for forward error correction using block codes.
Innovation Solution
A parallel circuit architecture that includes a register, a parallel combiner, and exclusive-or circuits to generate and check parity bits in parallel, utilizing a generator matrix to calculate partial parities and bit-wise exclusive-or operations across frames, enabling efficient processing of data blocks with high throughput and low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial implementation is used for generating and checking parity bits, then device complexity is reduced, but throughput is limited and cannot operate at line rates
Solution Approach 1:
The data block is divided into multiple frames, and the parity generation/checking process is segmented into parallel operations across these frames. Each frame is processed independently through separate exclusive-or circuits, enabling simultaneous computation that increases throughput while maintaining manageable circuit complexity through modular organization.
Solution Approach 2:
The patent transitions from serial processing (one-dimensional time sequence) to parallel processing by introducing a spatial dimension with multiple exclusive-or circuits operating simultaneously on different frames. This dimensional change allows the system to achieve line-rate operation by processing multiple data units concurrently rather than sequentially.
2Speed
If parallel circuit architecture is used to achieve high throughput, then processing speed increases, but device complexity increases
Solution Approach 1:
The parallel architecture is segmented into multiple exclusive-or circuits, each handling a specific frame. This segmentation allows the system to achieve high processing speed through parallel operations while controlling complexity by organizing circuits into discrete, manageable units that can be independently implemented and maintained.
Solution Approach 2:
The same exclusive-or circuit structure is universally applied across all frames, with each circuit performing identical parity generation/checking operations on its assigned frame. This multi-functional approach allows the system to achieve high speed through parallelism while reducing complexity by reusing the same circuit design pattern rather than creating unique circuits for each function.
3Loss of time
If parallel processing of frames is implemented, then latency is reduced, but the number of required circuits increases
Solution Approach 1:
The data stream is segmented into frames that can be processed in parallel, reducing the time each frame spends in the processing pipeline. By dividing the overall processing task into smaller frame-level segments handled by dedicated circuits, the system achieves lower latency while controlling circuit count through efficient frame-size selection and parallel processing architecture.
Solution Approach 2:
The system performs preliminary organization of data into frames before parallel processing begins. This preliminary action allows multiple frames to be prepared and fed into the parallel exclusive-or circuits simultaneously, reducing latency by eliminating sequential preparation overhead while keeping the number of circuits manageable through efficient frame batching and pipeline organization.
Data Source
AI summary
Methods and circuits process a data block of first bits. A circuit includes a register and a parallel combiner. The register is configured to store second bits. The second bits are iteratively a partial parity for each of multiple frames of the data block. The parallel combiner is coupled to the register and configured to generate a combination of bits from third bits and the second bits from the register. These third bits are iteratively those of the first bits within each of the frames of the data block. The circuit also includes respective exclusive-or circuits associated with the second bits. These exclusive-or circuits are coupled to the parallel combiner and the register. The respective exclusive-or circuit for each second bit is configured to generate the second bit from the combination of bits.