Parallel Partition Scheduling for Electromigration Analysis
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Solution Overview
Problem
Current circuit models oversimplify signal electromigration analysis, leading to inaccurate predictions and potential catastrophic failures due to overestimation of component density and overlooked signal combinations, resulting in costly re-modeling and retooling of manufacturing protocols.
Innovation Solution
A computer-implemented method for determining electromigration effects in integrated circuit models using parallel processing across multiple partitions, where a circuit netlist is divided into smaller partitions and scheduled across a network of computers for efficient simulation, allowing for refined analysis and reduced computational burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit models simplify the assumptions of signal flow to reduce computational complexity, then the computational burden is reduced, but the measurement precision of electromigration effects deteriorates due to overestimation and overlooking certain signal combinations
Solution Approach 1:
The circuit model is divided into multiple partitions, each processed independently by different computational threads. This segmentation allows the system to maintain detailed signal flow analysis for each partition while distributing the computational load across multiple processors, thereby preserving measurement precision without sacrificing productivity
Solution Approach 2:
The patent introduces parallel processing across multiple computational threads and partitions, adding a temporal and spatial dimension to the computation. This allows the system to perform detailed electromigration analysis on each partition simultaneously, maintaining accuracy while achieving computational efficiency through parallel execution rather than sequential processing
2Measurement precision
If large integrated circuits with billions of components are simulated with detailed signal flow, then the measurement precision of electromigration effects is improved, but the computational burden and loss of time increase significantly
Solution Approach 1:
The large integrated circuit is partitioned into multiple smaller sub-circuits, each processed by dedicated computational threads. This segmentation enables detailed electromigration analysis to be performed on manageable portions simultaneously, reducing the overall simulation time while maintaining comprehensive coverage of all components
Solution Approach 2:
Multiple computational threads process different partitions continuously and in parallel, eliminating idle time and maximizing resource utilization. The partition scheduler continuously assigns and manages tasks across available computational resources, ensuring that the detailed electromigration analysis proceeds without interruption across the entire circuit
3Device complexity
If oversimplified signal flow assumptions are used in circuit models, then the computational complexity is reduced, but the reliability of the circuit model deteriorates due to potential catastrophic failures from overlooked signal combinations
Solution Approach 1:
By dividing the circuit into partitions and analyzing signal combinations within each partition, the system maintains comprehensive signal flow analysis without requiring a monolithic complex model. Each partition can be processed with appropriate detail, ensuring reliable electromigration assessment while keeping individual model complexities manageable
Solution Approach 2:
The partition scheduler and computational thread management system act as intermediaries that coordinate detailed electromigration analysis across multiple partitions. This intermediary layer enables comprehensive signal combination analysis to be performed systematically across the entire circuit without requiring a single overly complex model, thereby maintaining reliability while managing complexity
Data Source
AI summary
A method for determining an electromigration effect in an integrated circuit model with multiple parallel processors is provided. The method includes receiving, in a partition scheduler, a circuit netlist divided into smaller partition netlists in a partition scheduler and scheduling a computational thread including tasks associated with a first partition netlist, and verifying that at least one task in the first computational thread has been executed by at least one computer selected from a network of computers. The method also includes releasing the computer and resetting a status of the computer, converting a result from the at least one task to an input file for another computational thread associated with a second partition netlist, the result including an induced current in the circuit component of the first partition netlist. The method includes determining electromigration effects on the circuit component in the partition netlists based on the induced current.