Parallel Path Cache Pre-staging for Storage Efficiency

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Solution Overview

Problem

Current storage systems face inefficiencies in pre-staging data into cache due to the time required for transmitting in-band cache hints and loading data into cache, which can take hundreds to thousands of microseconds, impacting performance and reliability.

Innovation Solution

The method involves utilizing parallel paths of differing performance by transmitting a first command over a faster path to prepare for and influence the execution of a second command over a slower path, optimizing data pre-staging and cache management by pre-populating the cache before the actual data request.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If in-band cache hints are transmitted over a conventional communication path, then the storage system can receive cache management instructions, but the transmission takes hundreds of microseconds causing delay

Engineering Contradiction:
Improvecache management accuracyVSAvoidhint transmission delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the cache management process into two independent parts: (1) sending the cache hint command over the faster PCIe path, and (2) sending the actual data transfer command over the traditional storage path. This segmentation allows the hint to be transmitted independently and in advance, eliminating the sequential dependency that caused the delay.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The storage system performs preliminary action by receiving and processing the cache hint command before the actual data transfer command arrives. The hint is processed in advance to pre-stage data in the cache, so when the data transfer command arrives, the data is already ready, eliminating the need to wait for hint processing during the data transfer.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If data is loaded into cache before delivery to application, then cache can improve I/O performance, but loading data into cache takes hundreds to thousands of microseconds

Engineering Contradiction:
ImproveI/O performanceVSAvoiddata loading time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system performs preliminary data staging in the cache based on the hint command received in advance. By processing the hint and pre-loading data into cache before the application's actual data request arrives, the system ensures that when the data is needed, it is already resident in the fast cache memory, eliminating the need for slow disk access at the moment of demand.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent separates the cache management operation (triggered by hint) from the data transfer operation. This allows the cache to be populated independently in advance, and the data transfer to proceed separately, with both operations overlapping in time rather than executing sequentially, thus hiding the data loading latency.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single communication path is used for both cache hints and data transfer, then system complexity is reduced, but efficiency is lost due to sequential processing

Engineering Contradiction:
Improvecommunication path structureVSAvoidoverall system efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the communication infrastructure into two separate paths: a fast path (PCIe) for control commands like cache hints, and a traditional path for data transfer operations. This segmentation allows each path to be optimized for its specific function and enables parallel processing of hint commands and data transfer commands, dramatically improving system throughput and efficiency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10664406B2Coordinated utilization of parallel paths to improve efficiency
Publication Date: 2020.05.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10664406B2 patent drawing
  • US10664406B2 patent drawing
  • US10664406B2 patent drawing

AI summary

A method for utilizing parallel paths of differing performance to improve efficiency is disclosed. In one embodiment, such a method includes transmitting, over a faster path, a first command to perform first actions intended to improve efficiency of second actions associated with a second command. The method transmits, over a slower path in parallel with the faster path, the second command. Alternatively, a method for utilizing parallel paths of differing performance to improve efficiency includes receiving, over a faster path, a first command to perform first actions intended to improve efficiency of second actions associated with a second command. The method executes the first command to perform the first actions. The method receives, over a slower path in parallel with the faster path, the second command and executes the second command to perform the second actions. Corresponding systems and computer program products are also disclosed.