Parallel Pattern Generators for High-Speed Memory Testing
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Solution Overview
Problem
Current automatic test equipment (ATE) for memory devices has limited test coverage and speed, making it inefficient for high-speed memory testing and increasing costs due to its complexity and restrictive pattern generation capabilities.
Innovation Solution
A memory test device with a sequencer that outputs multiple sequencer outputs to parallel pattern generators, allowing for variable test patterns and flexible execution of pattern commands, enabling improved test coverage and speed by generating multiple pattern memory addresses based on sequencer memory addresses and pattern commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single pattern generator is used in conventional ATE, then the device complexity is reduced, but the test coverage and speed are limited
Solution Approach 1:
The single pattern generator is segmented into multiple parallel pattern generators (first pattern generator and second pattern generator), each capable of independently generating test patterns. This segmentation enables simultaneous execution of multiple test patterns, thereby increasing test speed and coverage while maintaining manageable complexity through modular architecture
Solution Approach 2:
Multiple pattern generators are merged into a unified test system with a common sequencer and selector. The sequencer coordinates multiple pattern generators, and the selector intelligently chooses which pattern generator output to use, combining their capabilities to achieve high-speed testing without proportionally increasing overall system complexity
2Adaptability or versatility
If multiple pattern generators operate in parallel, then test coverage is expanded, but the device complexity increases
Solution Approach 1:
The sequencer is designed as a universal control unit that can manage multiple pattern generators with the same control logic and interface. This multi-functionality allows the sequencer to coordinate any number of pattern generators without requiring separate control circuits for each, thereby expanding test coverage while keeping the control architecture simple and reusable
Solution Approach 2:
The selector acts as an intermediary between multiple pattern generators and the rest of the test system. It receives outputs from multiple pattern generators and selectively passes one to the subsequent stages, simplifying the interface complexity by providing a single standardized output interface regardless of the number of parallel pattern generators
3Extent of automation
If conventional ATE is used for high-speed memory testing, then testing can be automated, but the cost increases due to complexity
Solution Approach 1:
The test system employs dynamic pattern selection where the selector can switch between different pattern generators based on real-time testing requirements. This dynamic operation allows the system to adapt to different test scenarios and memory speeds, providing automated high-speed testing capability with a flexible architecture that doesn't require over-engineering for all possible cases
Data Source
AI summary
A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.