Parallel PIM Memory Banks with Offset Addressing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current memory devices lack an efficient method to provide and process data for neural network computations, particularly in performing parallel calculation processing using processor-in-memory (PIM) circuits, where appropriate data and information are not adequately managed for neural network functions.

Innovation Solution

A memory device with multiple banks and corresponding PIM circuits, where each bank has a unique offset for parallel data reading and processing, allowing the control logic to manage memory operations and calculation processing by generating internal addresses for accessing different rows in each bank, enabling parallel calculation processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is read from multiple banks sequentially for calculation processing, then the memory device can provide data to PIM circuits, but the processing speed and efficiency are reduced due to lack of parallelism

Engineering Contradiction:

Improvecalculation processing speedVSAvoidtime for data reading and processing

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The memory device is divided into multiple independent banks (first bank, second bank, etc.), each with its own memory cell array. Each bank can be accessed independently and simultaneously, allowing parallel data retrieval. The control logic manages multiple banks separately, enabling concurrent reading operations that directly increase calculation processing speed while reducing time loss.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple banks are combined into a single memory device system with unified control logic. The control logic coordinates multiple banks to work together in parallel, merging their capabilities to provide data to multiple PIM circuits simultaneously. This combination enables the system to achieve higher overall productivity than individual banks could achieve separately.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If the memory device uses a single bank for calculation processing, then the structure is simpler, but the ability to perform parallel calculation processing is limited

Engineering Contradiction:

Improveparallel calculation capabilityVSAvoidnumber of banks and control logic

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Each bank is designed with universal functionality to perform the same memory operations and data provision tasks. The control logic is designed to manage multiple banks using the same control mechanisms, allowing the system to scale. This universality enables parallel calculation capabilities while keeping the added complexity manageable through standardized designs.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system transitions from a single-bank one-dimensional structure to a multi-bank parallel structure, adding a dimensional aspect of parallelism. By organizing banks in parallel rather than sequentially, the system gains the ability to perform multiple calculation operations simultaneously, significantly enhancing adaptability for parallel processing while the complexity increases in a controlled, structured manner.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If data is read from the same position in all banks, then the addressing is simpler, but the efficiency of neural network computations is reduced due to inability to access different data simultaneously

Engineering Contradiction:

Improveneural network computation efficiencyVSAvoidoffset configuration and address generation

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Each bank is configured with a unique offset value that determines its local data access pattern. The control logic uses these different offsets to read from different positions in each bank simultaneously, allowing each bank to provide different data to different PIM circuits. This local differentiation enables efficient neural network computations by allowing parallel access to diverse data while the offset configuration provides a systematic way to manage the added complexity.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11416178B2Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device

Publication Date: 2022.08.16 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.