Parallel Pin Grouping for IC Package Short Detection
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Solution Overview
Problem
Testing a large number of densely packed pins in chip scale packages for shorts and continuity is inefficient due to the inability to detect pin-to-pin shorts when testing multiple pins simultaneously, as existing methods rely on serial testing and cannot differentiate between proper continuity and shorts.
Innovation Solution
Implementing a parallel testing method where pins are grouped and tested in parallel, using a current source to force current through each pin and measuring voltage, with non-adjacent pins held at a reference voltage to detect shorts by distinguishing between diode drops and reference voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pins are tested in parallel simultaneously, then testing time is reduced, but pin-to-pin shorts cannot be detected
Solution Approach 1:
The patent segments the pins into multiple groups based on their spatial adjacency relationships. By dividing the pin array into non-adjacent groups, the testing method can apply different voltage levels to different groups, enabling both parallel testing and short detection. This segmentation resolves the contradiction by allowing simultaneous testing of multiple pins while maintaining the ability to detect shorts through group-based voltage differentiation.
Solution Approach 2:
The patent applies different voltage levels (first voltage level vs. second voltage level) to different pin groups based on their local spatial relationships. Non-adjacent pins are assigned one voltage level while adjacent pins are assigned another, creating local quality differences that enable short detection. This local differentiation allows the system to maintain high testing speed while accurately detecting pin-to-pin shorts.
2Reliability
If serial testing is used to detect shorts, then short detection accuracy is maintained, but testing time increases
Solution Approach 1:
The patent segments pins into multiple testable groups that can be tested in parallel. By organizing pins into groups where non-adjacent pins share the same voltage level, the system can test multiple groups simultaneously while still detecting shorts through voltage level comparison. This segmentation enables parallel processing without sacrificing short detection capability.
Solution Approach 2:
The patent dynamically assigns voltage levels to different pin groups based on their adjacency relationships. By switching between different voltage level configurations and testing multiple groups in parallel sequences, the system achieves both fast testing and accurate short detection, resolving the time-accuracy tradeoff of serial testing.
3Productivity
If all pins are tested at once, then productivity is improved, but false negatives occur due to adjacent pin shorts
Solution Approach 1:
The patent segments the pin array into multiple groups where pins in the same group are non-adjacent. This segmentation prevents false negatives by ensuring that pins tested simultaneously with the same voltage level are not adjacent, eliminating the possibility of undetected pin-to-pin shorts while maintaining high testing throughput through parallel group testing.
Solution Approach 2:
The patent applies different voltage levels to different pin groups based on their local spatial arrangement. By creating local quality differences in voltage assignment, the system can accurately distinguish between true continuity and pin-to-pin shorts even when testing multiple pins simultaneously, thereby maintaining measurement precision while improving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces testing time by allowing simultaneous continuity and short detection across multiple pins, ensuring all pins are verified for connectivity without false negatives due to adjacent pin shorts, thereby improving production efficiency.
Implementation Method 1
Each pin in the first group is tested for continuity by connecting a separate current source to the pin and measuring a resultant voltage on the pin
Data Source
AI summary
An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested.