Parallel Pipe Latch Circuitry for Faster ECC Memory Access
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Solution Overview
Problem
Error correction code (ECC) processes in memory devices introduce delays that affect memory access capabilities.
Innovation Solution
Implementing parallel pipe latch circuitry to maintain command data within the pipe latch circuitry for a duration longer than the error calculation time of the ECC circuitry, reducing delays by using parallel instead of series pipe latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) circuitry is implemented to perform corrections, then data integrity and reliability are improved, but memory access speed and capability deteriorate due to delays
Solution Approach 1:
The patent segments the memory access path into parallel lanes (first lane and second lane), allowing command data to be transmitted through multiple independent paths simultaneously. This segmentation enables the system to maintain ECC correction functionality while reducing overall access delay by distributing the data flow across parallel channels rather than forcing sequential processing through a single ECC stage.
Solution Approach 2:
The patent introduces a temporal dimension to the data path by implementing pipe latch circuitry that holds command data for extended periods. This allows the system to decouple the timing of command data arrival from the timing of ECC processing completion, enabling faster memory access by preparing data in advance and maintaining it in a ready state without requiring synchronous ECC processing at each access point.
2Stability of the object's composition
If series pipe latches are used to maintain command data, then data stability is improved, but access delay increases
Solution Approach 1:
The patent divides the single series pipe latch path into multiple parallel pipe latch lanes. Each lane maintains command data independently, providing the same stability function as a series configuration but without the cumulative delay of sequential processing. The parallel structure allows any lane to service access requests immediately without waiting for other lanes to complete their maintenance cycles.
Solution Approach 2:
The patent merges multiple parallel pipe latch lanes into a unified data structure that can be accessed by either the first or second lane. This combining approach maintains data stability through redundant parallel maintenance while enabling faster access by allowing any lane to service requests, effectively merging the stability benefits of series latches with the speed advantages of parallel processing.
Data Source
AI summary
A memory device comprises memory and control circuitry. The control circuitry can receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide command data of the command to pipe latch circuitry and error correction code (ECC) circuitry. The memory device further includes pipe latch circuitry to receive command data of the command from the control circuitry and maintain the command data for a period of time of a duration longer than error calculation time of the ECC circuitry.