Parallel Pipeline Hazard Avoidance Using Instruction Queues
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Solution Overview
Problem
Existing parallel processing units, such as GPUs, face challenges in efficiently tracking and eliminating inter-pipeline data hazards due to the complexity and cost of hardware-based detection, which is exacerbated by the need to manage multiple instruction pipelines operating in parallel.
Innovation Solution
A software-controlled method identifies inter-pipeline data hazards at compile time, using counters to track and enforce the appropriate ordering of instructions, and employs queue mechanisms to stall secondary instructions until associated hazards are resolved, with separate handling for low and high latency hazards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based detection is used to track inter-pipeline data hazards, then hazard detection capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces hardware-based detection mechanisms with a software-controlled approach. The compiler generates metadata tags that identify primary and secondary instructions, and the instruction decoder uses these tags to manage hazard tracking through counters and queues, eliminating the need for complex hardware detection circuits.
Solution Approach 2:
The patent performs hazard identification and instruction classification during the compile time phase. The compiler analyzes the instruction stream, identifies potential inter-pipeline data hazards, and embeds metadata tags in the instruction stream before execution, allowing the runtime system to efficiently manage hazards without complex hardware detection.
2Productivity
If multiple instruction pipelines operate in parallel to improve processing throughput, then productivity is improved, but inter-pipeline data hazard tracking becomes more difficult
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of metadata tags and counters that mediate between multiple instruction pipelines. The tags identify instructions involved in inter-pipeline hazards, and counters track the resolution status, enabling coordinated hazard management across parallel pipelines without direct complex inter-pipeline communication.
Solution Approach 2:
The patent replaces complex hardware-based inter-pipeline hazard tracking with a software-controlled system using metadata tags and queue mechanisms. The instruction decoder manages hazard tracking for multiple pipelines through software logic, reducing the need for complex hardware synchronization mechanisms.
3Reliability
If secondary instructions are stalled in queues to ensure correct execution order, then data hazard avoidance is improved, but execution time increases
Solution Approach 1:
The patent implements a feedback mechanism using counters that track the resolution status of data hazards. When a primary instruction completes and resolves a hazard, the counter is updated, automatically allowing stalled secondary instructions to proceed. This feedback-driven approach ensures correct execution order while minimizing unnecessary stalls.
Solution Approach 2:
The patent uses dynamic counter values to control the stalling of secondary instructions. Rather than static ordering, the system dynamically adjusts execution flow based on real-time hazard resolution status tracked by counters, allowing secondary instructions to be unstalled as soon as their dependencies are satisfied.
Data Source
AI summary
Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.