Image Processing Apparatus Parallel Pixel Scaling

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Solution Overview

Problem

Existing image processing apparatuses in printers and facsimile machines face inefficiencies in scaling low-resolution images to match the resolution of plotter engines, particularly when magnification factors are real numbers with decimals, leading to suboptimal processing speed and accuracy.

Innovation Solution

The apparatus calculates and stores pixel scale factors for each pixel position in the main scanning direction based on magnification, allowing for parallel reading and multiplication of pixel data, enhancing processing speed through the use of multiple scaling units and optimized memory configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If sequential processing of pixel scaling is used, then processing accuracy is maintained, but processing speed deteriorates

Engineering Contradiction:
Improvescaling accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the scaling operation into two independent parts: (1) pre-calculation of pixel scale factors stored in memory, and (2) parallel multiplication of pixel values by their corresponding scale factors. This segmentation allows the computationally intensive scaling factor calculations to be performed once and reused, enabling parallel processing of multiple pixels simultaneously while maintaining accuracy through the use of precise pre-calculated factors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary calculation and storage of pixel scale factors before the actual scaling operation. By pre-computing the scale factors based on the magnification ratio and storing them in memory ordered by pixel position, the system prepares all necessary scaling parameters in advance, enabling subsequent parallel processing operations to proceed at high speed without compromising accuracy.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If parallel processing is implemented, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent uses a memory structure that stores copied pixel scale factors in the same order as pixel positions. By creating this ordered copy of scale factors in memory, the system enables parallel reading of multiple pixel values and their corresponding scale factors simultaneously, achieving high-speed parallel processing while keeping the hardware architecture relatively simple through the use of standard memory structures.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent implements a universal scaling architecture where the same memory structure and processing units can handle different magnification ratios and image sizes. The system uses a single set of processing units that can process any number of pixels in parallel by simply changing the input image data and corresponding scale factors, avoiding the need for multiple specialized processing paths.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10692180B2Image processing apparatus
Publication Date: 2020.06.23 RICOH CO LTD
  • US10692180B2 patent drawing
  • US10692180B2 patent drawing
  • US10692180B2 patent drawing

AI summary

An image processing apparatus includes a memory and circuitry. The circuitry is configured to calculate a pixel scale factor for each of pixel positions in a main scanning direction of an input image for a line based on a magnification. The circuitry is configured to store, in the memory, the pixel scale factors calculated for the line in order of pixel position. The circuitry is configured to read, in parallel, N-number of pixel scale factors of the pixel scale factors for the line in order of pixel position from the memory, in synchronization with parallel reading of N-number of pixels in the main scanning direction from the input image, where N represents an integer not smaller than 2. The circuitry is configured to multiply, in parallel, the N-number of pixels read from the input image by the respective N-number of pixel scale factors read from the memory.