Parallel Plate Capacitors in Stacked Semiconductor Dies
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Solution Overview
Problem
Conventional methods for improving power delivery in stacked semiconductor devices often require increasing the size of semiconductor dies by increasing the TSV count, which is inefficient in reducing resistance and meeting high power demands, especially for uppermost dies in the stack.
Innovation Solution
Incorporating parallel plate capacitors between adjacent semiconductor dies in the stack, formed as part of existing metallization processes, to store charge locally and address power spikes without increasing the size or TSV count of the dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the TSV count of semiconductor dies is increased to reduce resistance and improve power delivery, then power delivery capability is improved, but the size of semiconductor dies must be increased
Solution Approach 1:
The patent introduces a vertical stacking dimension to the power delivery architecture by forming capacitors between adjacent semiconductor dies in the stack. This utilizes the third dimension (vertical space between dies) to provide additional power delivery capability without increasing the planar footprint of individual dies. The capacitors are formed in the inter-die space, effectively moving the power delivery solution from a 2D plane to a 3D volumetric approach.
Solution Approach 2:
The patent introduces capacitors as intermediary energy storage elements between the power supply and the semiconductor dies. These capacitors act as local energy reservoirs that can quickly discharge to meet power spikes, mediating between the external power supply and the high-power-demanding dies. This intermediary approach allows power delivery improvement without requiring increased TSV count or die size.
2Device complexity
If conventional power delivery methods are used in stacked semiconductor devices, then device complexity is maintained, but power delivery to uppermost dies is insufficient for high power operations
Solution Approach 1:
The patent segments the power delivery function into multiple distributed capacitive elements located at different levels of the stack. Instead of relying on a single centralized power delivery path, the system divides power storage and delivery across multiple inter-die capacitors. This segmentation allows each local capacitor to serve its adjacent dies, improving power delivery to uppermost dies while maintaining overall structural simplicity through modular replication of the same capacitor structure throughout the stack.
3Speed
If external power supply response time is reduced to meet power spikes, then power delivery speed is improved, but the response time of external power supplies cannot be sufficiently reduced
Solution Approach 1:
The patent implements preliminary action by pre-charging capacitors during low-power intervals so that energy is already stored and ready for immediate discharge when power spikes occur. The capacitors are continuously maintained at a charged state during normal operation, performing the energy accumulation action in advance before it is needed. This eliminates the need for rapid external power supply response, as the local capacitors can instantly provide the required power surge.
4Power
If TSV count is increased to improve power delivery, then power network resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the capacitor formation process with the existing metallization processes used in semiconductor manufacturing. The capacitors are formed using the same deposition and patterning tools and techniques already employed for creating interconnect structures. By combining the capacitor fabrication into the existing metallization flow, the patent avoids adding separate manufacturing steps, thereby improving power network resistance without significantly increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances power delivery and signal integrity by providing a localized power source that can quickly meet short-term power demands, reducing the need for external power supply response time and minimizing inductive ringing, while maintaining the compact size of semiconductor die stacks.
Implementation Method 1
Incorporating parallel plate capacitors between adjacent semiconductor dies in the stack, formed as part of existing metallization processes, to store charge locally and address power spikes
Data Source
AI summary
Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.