Parallel Plate Wiring Boards for Low Inductance Power Modules
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Solution Overview
Problem
In power semiconductor modules, large wiring inductance leads to increased switching loss and potential device destruction or electromagnetic interference noise, especially during high-speed switching operations.
Innovation Solution
The design incorporates a power semiconductor module with parallel plate-shaped wiring boards surrounding Schottky barrier diodes, where the mutual inductance of the wiring boards cancels out self-inductance, reducing internal inductance and switching loss, and includes features like dielectric layers, slits, and bonding wires to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wiring structures are used in power semiconductor modules, then the module structure is simple and easy to manufacture, but the wiring inductance becomes large leading to increased switching loss
Solution Approach 1:
The patent combines multiple wiring boards into a integrated structure where the first and second wiring boards are positioned adjacent to each other with parallel plate-shaped portions. This merging approach allows the wiring structure to simultaneously perform multiple functions: providing electrical connections, reducing inductance through mutual inductance cancellation, and dissipating heat. The combined structure eliminates the need for separate inductance-reduction components while achieving low inductance characteristics.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar wiring to a three-dimensional stacked configuration. The plate-shaped portions of the wiring boards extend in multiple dimensions with specific orientations (first plate-shaped portion parallel to second plate-shaped portion, both perpendicular to substrate). This dimensional change enables mutual inductance cancellation between adjacent wiring boards while maintaining compact module size, effectively reducing wiring inductance without proportionally increasing module volume.
2Reliability
If wiring inductance is reduced through complex wiring structures, then switching loss decreases, but the module complexity and manufacturing difficulty increase
Solution Approach 1:
The patent incorporates dielectric layers and slits into the wiring board structure during the manufacturing process, before the module is assembled and put into service. The dielectric layers are pre-formed between wiring boards, and slits are pre-cut in the plate-shaped portions. These preliminary structural features automatically provide insulation and control current paths, ensuring reliable operation without requiring complex post-assembly adjustments or specialized manufacturing techniques.
Solution Approach 2:
The wiring boards are divided into distinct functional segments: plate-shaped portions for current conduction, dielectric layers for insulation, and slits for current path control. This segmentation allows each component to be manufactured and optimized independently using standard PCB fabrication techniques, then assembled into the complete low-inductance wiring structure. The segmented approach simplifies manufacturing while achieving the complex function of inductance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces internal inductance, minimizes switching loss, and improves the reliability of the power semiconductor module by suppressing current variations and device destruction, while allowing for efficient heat dissipation and reduced electromagnetic interference.
Implementation Method 1
the mutual inductance of the wiring boards cancels out self-inductance, reducing internal inductance
Data Source
AI summary
A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion.