Parallel Fractional-N PLL Using DLL References for Fast FMCW Chirps
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Solution Overview
Problem
Conventional FMCW radar sensors face limitations in achieving precise range and Doppler measurements due to the linearity of the chirp signal, particularly at higher operating frequencies, where the maximum operating frequency of phase and frequency detectors restricts the frequency multiplication factor, leading to noise and phase errors that degrade measurement accuracy.
Innovation Solution
A phase locked loop (PLL) circuit architecture that incorporates a delay locked loop (DLL) to generate multiple phase-shifted reference signals, allowing for parallel fractional-N dividers and phase frequency detectors, which enables precise phase and frequency detection without increasing the operational frequency of detectors, thereby reducing noise and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency multiplication factor is increased to improve measurement precision, then the operational frequency of phase and frequency detectors must be increased, but this exceeds the maximum operating frequency limit of the detectors
Solution Approach 1:
The patent divides a single high-frequency detection task into multiple parallel lower-frequency detection tasks. By using multiple phase-frequency detectors operating in parallel at lower frequencies, the system achieves the equivalent of high-frequency detection without exceeding the maximum operating frequency limit of individual detectors, thereby maintaining measurement precision while respecting detector frequency constraints.
2Measurement precision
If parallel phase frequency detectors are used to reduce noise and improve linearity, then the device complexity increases due to multiple dividers and detectors
Solution Approach 1:
The patent combines multiple parallel detection paths into a unified system where the outputs of multiple phase-frequency detectors are summed or combined to produce a final control signal. This merging approach allows the system to benefit from the noise reduction and linearity improvement of parallel detection while managing complexity through systematic integration of the multiple components.
Data Source
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AI summary
Novel phase locked loop architectures that can overcome the limitation of the maximum operating frequency of the fractional-N phase-locked loop (PLL) for fast-chirp frequency modulated continuous wave (FMCW) radars are suggested. Several phase frequency detector and charge pumps (PFD&CPs) are put in parallel and are operated with reference signals that are generated by using a delay-locked loop (DLL) instead of further increasing the operating frequency of the PFD&CP. The proposed DLL supported parallel PLL architectures enable further speeding up the FMCW chirp as well as improving its linearity and the performance of Range Doppler Radars based on fast-chirp FMCW radar. Methods for operating the parallel fractional N phase locked loop are proposed.