Parallel Fractional-N PLL Using DLL References for Fast FMCW Chirps
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Solution Overview
Problem
Conventional FMCW radar sensors face limitations in achieving precise range and velocity measurements due to the linearity of the chirp signal, particularly at higher operating frequencies, where the maximum operating frequency of phase frequency detectors and charge pumps restricts the frequency multiplication factor, leading to noise and phase errors.
Innovation Solution
A phase locked loop (PLL) circuit with a delay locked loop as the reference signal source, utilizing multi-modulus dividers, delta sigma modulators, and parallel phase frequency detectors and charge pumps to generate multiple phase-shifted reference signals, which are compared to control the voltage controlled oscillator, allowing for reduced noise levels and increased precision without increasing the operational frequency of detectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the operating frequency of the PLL is increased to improve measurement precision, then the linearity of the chirp signal improves, but the maximum operating frequency of phase frequency detectors and charge pumps is exceeded, leading to noise and phase errors
Solution Approach 1:
The patent divides a single high-frequency PLL loop into multiple parallel lower-frequency PLL loops. Each parallel loop operates at a reduced frequency that is within the reliable operating range of phase frequency detectors and charge pumps, thereby maintaining loop reliability while collectively achieving the desired high-frequency measurement precision through parallel operation
Solution Approach 2:
The patent transitions from a single-dimensional high-frequency operation to a multi-dimensional parallel architecture. By introducing multiple parallel PLL loops operating at lower frequencies, the system achieves the functional equivalent of high-frequency operation without exceeding the maximum operating frequency limits of individual detector and charge pump components
2Measurement precision
If the frequency multiplication factor is increased to achieve higher operating frequencies, then the measurement precision improves, but the maximum operating frequency of phase frequency detectors and charge pumps restricts further multiplication
Solution Approach 1:
The patent segments the frequency multiplication function across multiple parallel PLL loops. Instead of using a single high multiplication factor that would exceed detector and charge pump limits, each parallel loop uses a lower multiplication factor operating within reliable frequency ranges, collectively achieving the desired high output frequency
Solution Approach 2:
The patent combines multiple parallel PLL loops to achieve the functional equivalent of a single high-frequency system. By merging the outputs of multiple lower-frequency loops, the system achieves high operating frequencies and measurement precision without requiring any single detector or charge pump to operate beyond its maximum frequency capability
Data Source
AI summary
Novel phase locked loop architectures that can overcome the limitation of the maximum operating frequency of the fractional-N phase-locked loop (PLL) for fast-chirp frequency modulated continuous wave (FMCW) radars are suggested. Several phase frequency detector and charge pumps (PFD&CPs) are put in parallel and are operated with reference signals that are generated by using a delay-locked loop (DLL) instead of further increasing the operating frequency of the PFD&CP. The proposed DLL supported parallel PLL architectures enable further speeding up the FMCW chirp as well as improving its linearity and the performance of Range Doppler Radars based on fast-chirp FMCW radar. Methods for operating the parallel fractional N phase locked loop are proposed.