Parallel Phase Detection in PLLs for Lower Reference Noise
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Solution Overview
Problem
Designing RF oscillators with low phase noise at millimeter-wave frequencies is challenging due to degraded capacitor quality factors and increased parasitics, leading to increased power consumption and chip area, and increasing PLL bandwidth to reduce phase noise results in higher reference path noise.
Innovation Solution
A phase locked loop (PLL) system utilizing multiple parallel matched phase detection circuits to compare the phase of a reference signal with a clock signal, filtering the combined phase detection signals to form a filtered phase detection signal, and using this signal to control the frequency of an oscillator, thereby reducing noise generated by the phase detection function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bandwidth of a PLL is increased to reduce phase noise generated by the RF oscillator, then the phase noise performance is improved, but the reference path noise increases
Solution Approach 1:
The single phase detection function is segmented into multiple parallel phase detection circuits. Each circuit independently compares the reference signal with the divided clock signal, and their outputs are combined. This segmentation allows the system to achieve better noise performance by averaging out reference path noise across multiple independent detection paths while maintaining the ability to suppress oscillator phase noise through the feedback loop.
2Measurement precision
If RF oscillators are designed with low phase noise characteristic at millimeter wave frequencies, then the phase noise performance is improved, but the power consumption and chip area increase
Solution Approach 1:
Multiple phase detection circuits serve as intermediary elements that process the phase comparison function. By distributing the phase detection task across multiple circuits with identical topology, the system achieves improved phase noise performance without requiring the RF oscillator itself to be redesigned with more complex and power-consuming low-noise components. The intermediary phase detection circuits handle the noise reduction function.
3Measurement precision
If RF oscillators are designed with low phase noise characteristic at millimeter wave frequencies, then the phase noise performance is improved, but the chip area increases
Solution Approach 1:
The phase detection function is segmented into multiple parallel circuits, each with identical topology. This segmentation approach achieves better phase noise performance through statistical averaging without requiring a single large, complex low-noise oscillator design. The total chip area is distributed across multiple simple, identical circuits rather than concentrated in one complex circuit, potentially improving area efficiency while achieving the noise performance goal.
Data Source
AI summary
In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.