Parallel Polar Encoder Architecture for 5G Control Channel Throughput
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Solution Overview
Problem
Current wireless communication systems, particularly in 5G NR, face challenges in achieving high throughput and low latency while maintaining efficient hardware resource utilization, especially in channel encoding processes like CRC interleaving, polar encoding, and rate matching.
Innovation Solution
The proposed solution involves a flexible and parallelizable hardware architecture for the channel encoding chain, incorporating a polar encoder based on radix-k processing and FFT concepts, along with efficient CRC interleavers and rate matchers, optimized for low resource consumption and high throughput, specifically designed for 5G NR PDCCH applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional channel encoding processes are used in 5G NR, then basic communication functionality is achieved, but hardware resource consumption increases and throughput decreases
Solution Approach 1:
The channel encoding process is divided into independent parallel stages: CRC attachment stage, interleaving stage, and polar encoding stage. Each stage processes different bit groups simultaneously using separate hardware resources, enabling parallel execution that increases throughput while maintaining manageable hardware complexity at each stage.
Solution Approach 2:
The patent introduces time-parallel processing dimension by processing multiple bit groups simultaneously across different stages. The interleaving stage operates on multiple bit groups in parallel, and the polar encoding stage processes different code blocks concurrently, transforming sequential processing into parallel operations across the time dimension.
2Productivity
If high-throughput encoding is implemented, then data rate increases, but hardware complexity increases
Solution Approach 1:
The encoding system is segmented into independent functional blocks (CRC attachment, interleaving, polar encoding) that can be implemented with dedicated hardware resources. Each block processes specific portions of the data stream in parallel, achieving high aggregate throughput without requiring each individual block to be overly complex.
Solution Approach 2:
The hardware architecture uses universal processing units that can handle multiple functions across different encoding stages. The same types of processing resources are reused across CRC attachment, interleaving, and polar encoding operations, reducing overall hardware complexity while maintaining high throughput through efficient resource utilization.
Data Source
AI summary
Example implementations include a method, apparatus and computer-readable medium of wireless communications, comprising receiving an input data sequence of a set of bits, wherein the input data sequence includes at least a portion of a set of CRC interleaved information bits, and wherein a number of the set of bits is at least 32. The implementations further include encoding the input data sequence by a polar encoder to define an intermediate polar encoded data sequence, the polar encoder having a combinational circuit including a plurality of stages that operate in a same clock cycle. Additionally, the implementations further include encoding the intermediate polar encoded data sequence for each of the plurality of stages according to a polar encoder factor graph to obtain a final polar encoded data sequence. Additionally, the implementations further include transmitting a polar encoded codeword on a control channel based on the final polar encoded data sequence.