Parallel Polynomial Evaluation Circuit Architecture
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Solution Overview
Problem
Conventional electronic circuits for evaluating polynomials are slow, especially for high-degree polynomials, due to the need for a large number of iterations, which increases calculation time.
Innovation Solution
The proposed device uses multiple electronic circuits to simultaneously evaluate sub-polynomials, reducing the number of iterations required by subdividing the polynomial into K sub-polynomials and using a secondary circuit to combine the results, thereby accelerating the polynomial evaluation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a dedicated circuit implements the Homer algorithm with a single processing unit, then the circuit structure is simple, but the calculation time increases significantly for high-degree polynomials
Solution Approach 1:
The polynomial evaluation is divided into K independent sub-polynomial evaluations, each processed by a separate circuit. The original polynomial of degree N is segmented into K sub-polynomials of degree (N+1)/K - 1, allowing parallel processing that reduces total calculation time while maintaining manageable circuit complexity for each segment.
Solution Approach 2:
The invention transitions from sequential processing in a single dimension to parallel processing across multiple dimensions by deploying K identical circuit structures simultaneously. Each circuit operates independently on its assigned sub-polynomial, effectively adding a parallelism dimension to the evaluation process.
2Productivity
If multiple circuits are used to simultaneously evaluate sub-polynomials, then the calculation speed increases, but the device complexity increases
Solution Approach 1:
K identical circuit structures are used, where each circuit is a universal module capable of evaluating any sub-polynomial of degree (N+1)/K - 1. This modular approach allows the same circuit design to be replicated K times, achieving parallel processing capability while maintaining design simplicity and reducing the complexity of individual circuit units.
3Quantity of substance
If the polynomial degree N is high, then more coefficients need to be processed, but the calculation time increases proportionally
Solution Approach 1:
The set of N+1 polynomial coefficients is segmented into K groups, with each group containing G = (N+1)/K coefficients. Each circuit processes one group independently, reducing the number of iterations per circuit from N to (N+1)/K - 1, thereby processing a larger total number of coefficients without proportionally increasing the time per circuit.
Data Source
AI summary
A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.