Hardware Accelerator for Parallel Poseidon Hash Computation

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Solution Overview

Problem

Existing hash functions, such as the Message Digest (MD) family, are no longer secure with the advancement of computer hardware, and more sophisticated hash functions like Poseidon are needed for zero-knowledge proof systems, but their computation is inefficient and time-consuming, especially for large input strings.

Innovation Solution

A hardware accelerator is developed to perform algebraic hash functions like Poseidon using parallel processors and a Merkle tree structure, optimizing computation through a combination of multiplications and additions, with a novel ring structure for efficient processing of large input strings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If more sophisticated hash functions like Poseidon are used for zero-knowledge proof systems, then security is improved, but computation efficiency deteriorates

Engineering Contradiction:
ImprovesecurityVSAvoidcomputation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The input string is divided into multiple blocks that are processed in parallel by multiple processors. Each processor handles a specific block independently, allowing simultaneous computation of hash values for different segments. This segmentation enables the system to maintain high security through sophisticated hash functions while improving overall computation efficiency through parallel processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from sequential single-processor computation to a multi-dimensional parallel processing architecture. Multiple processors operate simultaneously on different input blocks, adding a temporal and spatial dimension to the computation. This dimensional expansion allows the system to execute sophisticated hash functions across multiple processing units, resolving the contradiction between security requirements and computation efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If hash functions are applied to large input strings, then comprehensive processing is improved, but computational time increases

Engineering Contradiction:
Improveinput string sizeVSAvoidcomputational time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

Large input strings are segmented into smaller blocks that can be processed independently and in parallel. Each processor receives a specific block and computes its hash value simultaneously with other processors handling different blocks. This segmentation approach enables comprehensive processing of large input volumes while maintaining reduced computational time through concurrent execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The input string is pre-processed and divided into blocks before being distributed to multiple processors. This preliminary segmentation prepares the data for parallel computation, allowing the system to handle large input volumes efficiently by establishing the processing structure in advance rather than sequentially during the hashing operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12461786B2Hardware accelerator for computing an algebraic function
Publication Date: 2025.11.04 INGONYAMA LTD
  • US12461786B2 patent drawing
  • US12461786B2 patent drawing
  • US12461786B2 patent drawing

AI summary

A multi-thread processor computes a function requiring only modular additions and multiplications. Memories store constants, multi-bit elements, and multiple instruction sets. A multiplier receives first and second multiplier operands, generates their product, which is fed to an adder as a first operand and added to a second adder operand, the sum being stored in an accumulator memory. Each instruction set is executed on a successive clock, and includes instructions for defining respective addresses in the memories from which constants, elements and sums are to be accessed. A scheduler maintains a schedule of threads executable by the processor in parallel, and is configured on each successive clock to cycle through the threads and initiate a first available thread. Selectors responsive to instructions received from the program memory select the required multiplier and adder operands. A multi-core system executes multiple parallel threads on multiple processors allowing complex functions to be computed efficiently.