Parallel Power Semiconductor Gate Voltage Control
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Solution Overview
Problem
The existing systems for high voltage direct current (HVDC) light substations face issues with the short circuit failure mode (SCFM) of power semiconductor chips, where the low ohmic connection formed by aluminum plates decomposes over time, leading to increased voltage and potential arching, which can damage coolers and cause water leakage.
Innovation Solution
A system and method that involves monitoring power semiconductor chips connected in parallel, applying a higher gate voltage to the remaining chips when a failure is detected, reducing their resistance and enabling them to handle increased current loads, thereby extending the SCFM lifetime and preventing damage from short circuit overload events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If aluminum plates are used to form a low ohmic connection in SCFM, then the short circuit failure mode capability is achieved, but the connection decomposes over time leading to increased voltage and potential arching
Solution Approach 1:
The patent changes the electrical parameters (gate voltage, collector-emitter voltage) dynamically in response to detected failures. When a chip failure is detected, the system increases the third gate voltage above the second gate voltage and increases the third collector-emitter voltage above the second collector-emitter voltage, thereby changing the operating state of remaining chips to handle the increased current load and extend the low ohmic connection lifetime.
2Duration of action of stationary object
If the low ohmic connection is maintained for extended period, then SCFM lifetime is increased, but voltage increase causes arching and damage to cooler
Solution Approach 1:
The patent implements a feedback mechanism where the control means continuously monitors the operational state of power semiconductor chips. When a failure is detected, the system responds by adjusting gate voltages and collector-emitter voltages of remaining chips, creating a closed-loop control that adapts to the degraded system state and prevents harmful arching conditions.
Solution Approach 2:
The patent applies preliminary protective actions by pre-configuring the control means to detect chip failures and automatically adjust operating parameters before arching can occur. The system proactively increases voltages to redistribute current load among remaining functional chips, preventing the voltage buildup that would lead to arching and cooler damage.
3Reliability
If more power semiconductor chips are connected in parallel, then the current load per chip is reduced, but the complexity of the system increases
Solution Approach 1:
The patent implements a universal control approach where a single control means manages multiple power semiconductor chips with identical control logic. The same voltage adjustment mechanism applies to all chips regardless of their individual state, simplifying the control architecture while maintaining the ability to handle parallel chip configurations and failure scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the lifespan of the SCFM transition and prevents damage by allowing the remaining chips to handle the current load without overheating, ensuring the system survives until the next maintenance interval and reducing the risk of water leakage.
Implementation Method 1
applying a higher gate voltage to the remaining chips when a failure is detected, reducing their resistance
Implementation Method 2
the aluminium plate of this IGBT melts with the chip and also this IGBT goes into a low ohmic state
Implementation Method 3
the increased voltage can lead to arching and consequently to high energy dissipation during an SCFM transition
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
The system according to the invention comprises at least two power semiconductor chips (1,2,3,4) being connected in parallel and comprising each a gate terminal for switching the power semiconductor chip (1,2,3,4) in a blocking-state by a first gate voltage and for switching the power semiconductor chip (1,2,3,4) in a conducting- state by a second gate voltage. The system comprises further a control means (16,57) adapted for applying the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips (1,2,3,4). The control means (16) is adapted for applying a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip (1,2,3,4) when a power semiconductor chip (1,2,3,4) fails, and that the third gate voltage is higher than the second gate voltage.