Parallel Power Switches: Alternating Control for Load Balancing
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Solution Overview
Problem
Power semiconductor switches connected in parallel experience uneven loading due to component tolerances and different switching times, leading to premature failure and reduced system robustness.
Innovation Solution
A method and control unit that generate individual control signals for power semiconductor switches to alternate their switching times, ensuring even distribution of switch-on, switch-off, and power line losses across the switches, allowing for targeted load management and optimal utilization of all switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power semiconductor switches are connected in parallel to handle higher currents, then the current-carrying capacity of the system is improved, but uneven loading due to component tolerances and different switching times causes individual switches to be overloaded and fail prematurely
Solution Approach 1:
The patent applies periodic action by alternately switching individual power semiconductor switches on and off in a cyclic manner. The control unit generates individual control signals that cause switches to operate in alternating periods, ensuring that no single switch bears the full load continuously. This periodic switching pattern distributes thermal and electrical stress evenly across all parallel-connected switches, preventing premature failure while maintaining high current-carrying capacity.
Solution Approach 2:
The patent implements preliminary action by introducing advance timing offsets in the control signals before the switches would naturally switch due to component tolerances. The control unit compensates for anticipated switching time differences by pre-adjusting the trigger timing of individual switches. This preliminary correction ensures synchronized operation and prevents any single switch from being overloaded before the uneven loading can occur.
2Speed
If individual power semiconductor switches switch on at different times due to component tolerances, then the switching operation is completed, but the fastest and most sensitive switch bears a larger part of turn-on, turn-off and power line losses
Solution Approach 1:
The patent employs feedback mechanisms where the control unit monitors the actual switching behavior and performance of each parallel-connected power semiconductor switch. Based on this feedback information about switching times and loss distribution, the control unit dynamically adjusts the individual control signals to optimize the switching pattern. This feedback loop ensures that switches with faster switching speeds do not consistently bear disproportionate losses, as the control system compensates by adjusting timing or duty cycles.
Solution Approach 2:
The patent applies parameter changes by dynamically modifying the control parameters (timing, duty cycle, amplitude) of individual switch control signals based on observed performance. The control unit adjusts these parameters to equalize the energy losses across all switches, transforming the fixed, unequal loss distribution into a variable, balanced distribution through continuous parameter optimization.
3Device complexity
If a common control signal is used for all parallel-connected power semiconductor switches, then the control system is simple, but all switches cannot be evenly loaded due to different switching characteristics
Solution Approach 1:
The patent applies segmentation by dividing the single common control signal into multiple individual control signals, each tailored to a specific parallel-connected power semiconductor switch. This segmentation allows the control system to address the unique switching characteristics of each switch while maintaining an organized control structure. The control unit generates separate control signals with individual timing and parameter adjustments, enabling precise control over each switch to achieve uniform loading without requiring a completely complex decentralized control architecture.
Data Source
Figure 1
Figure 2~3
AI summary
The invention relates to a method (200) and a control device (1) for controlling at least two power semiconductor switches (LHS1..LHSn) connected in parallel for switching a total current (I_ges). The at least two power semiconductor switches (LHS1..LHSn) connected in parallel each have a gate terminal for controlling the respective power semiconductor switch (LHS1..LHSn). An input terminal (EA) for feeding the total current (I_ges), an output terminal (AA) for discharging the total current (I_ges), and a joint control terminal (S) for receiving a joint control signal (SI) that has the state 'disconnect' or 'connect' are provided. The at least two power semiconductor switches (LHS1..LHSn) connected in parallel are connected to the input terminal (EA) at the input end and to the output terminal (AA) at the output end. At least one ascertainment unit (EE) is designed to receive the joint control signal (SI) at the input end, ascertain at least two individual control signals (SI1..SIn) in accordance with the joint control signal (SI) in order to control the at least two power semiconductor switches (LHS1..LHSn), and output the at least two ascertained individual control signals to the gate terminals of the at least two power semiconductor switches at the output end. The at least two individual control signals (SI1..SIn) each have the state 'disconnect' or 'connect' and differ at least temporarily.