Parallel Power Switch Timing Compensation
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Solution Overview
Problem
In power converters with parallel connected power semiconductor switching devices, such as IGBTs, existing control methods lead to poor current sharing and synchronism due to timing variances and unequal device characteristics, resulting in reduced reliability and increased costs due to derating and the need for additional modules.
Innovation Solution
A circuit and method that includes drive modules with timing circuitry to compare switching delays with reference delays, and delay circuitry to adjust switching commands, ensuring synchronized switching by reducing time differences between devices, thereby improving current sharing and synchronism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If simple switching control is used for parallel devices, then device operation is straightforward, but current sharing and synchronism deteriorate due to timing variances
Solution Approach 1:
The patent implements feedback by measuring the actual switching delay of each parallel device and using this information to adjust the triggering signal timing. The system continuously monitors switching delays and dynamically compensates for variations, ensuring synchronized operation and improved current sharing while maintaining operational simplicity.
Solution Approach 2:
The patent changes the timing parameter of the triggering signal dynamically based on measured switching delays. By adjusting the triggering timing for each device according to its specific characteristics, the system achieves synchronized switching and optimal current sharing without complicating the overall control architecture.
2Reliability
If timing compensation is implemented to improve synchronism, then current sharing improves, but device complexity increases due to additional timing circuitry
Solution Approach 1:
The patent implements self-service by having each device measure its own switching delay and autonomously adjust its triggering timing. This distributed approach eliminates the need for complex centralized timing control circuitry, reducing overall system complexity while achieving improved synchronism and current sharing through local adaptive compensation.
3Reliability
If derating is applied to ensure reliable operation, then device reliability improves, but the number of modules required increases
Solution Approach 1:
The patent uses feedback-based timing compensation to achieve precise synchronism and optimal current sharing among parallel devices. This ensures that each device operates within its full capability range, eliminating the need for conservative derating and reducing the total number of modules required to meet system power requirements.
Data Source
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Figure 3a~3b
AI summary
The invention generally relates to methods and circuits for controlling switching of parallel coupled power semiconductor switching devices (3), for example for use in a power converter. In an example, there is provided a circuit for controlling switching of parallel coupled power semiconductor switching devices (3), the circuit comprising: a plurality of drive modules (2), each said module for controlling a said power semiconductor switching device (3); control circuitry to transmit switch command signals to the modules, each said switch command signal to trigger a said drive module to control a said power semiconductor switching device to switch state; and voltage isolation between the drive modules and the control circuitry, wherein each said drive module for controlling a said device comprises: timing circuitry (22) to compare a switching delay of the device and a reference delay, wherein said switching delay is a time interval between detecting a said switching command signal at the drive module and switching of the device in accordance with the detected switching command signal; and delay circuitry (21) to provide a controllable delay to delay a said triggering by a said switching command signal received at the module subsequent to the detected switching command signal, the delay circuitry configured to control the controllable delay according to a result of said comparison of said switching delay of the device, to thereby reduce a time difference between the reference delay and a said switching delay of the device switching in accordance with the subsequent switching command signal.