Parallel PRBS Circuit Tap Reduction for High-Speed Routing

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Solution Overview

Problem

Conventional circuits for generating high-speed parallel pseudo-random binary sequences (PRBSs) face challenges due to the need for extensive routing, leading to increased complexity and difficulty in meeting speed and timing requirements, particularly in high-speed digital interfaces like telecommunications and data communications.

Innovation Solution

The method involves generating M parallel PRBSs using a circuit with a reduced number of taps by loading an initial M-bit word and repeatedly generating the next M-bit word using at least n+1 sequential bits, with the option to omit taps in favor of equivalent logical combinations, thereby reducing the number of taps required in the circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If parallel PRBS generation is implemented to achieve high-speed data generation, then the generation speed is improved, but the routing complexity and circuit difficulty increase substantially

Engineering Contradiction:
ImprovePRBS generation speedVSAvoidrouting complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the PRBS generation process by dividing the 31-bit PRBS sequence into multiple parallel streams. Each stream is generated by a dedicated tap combination, allowing simultaneous processing of multiple bits. This segmentation enables high-speed generation while managing routing complexity through structured organization of tap connections across parallel paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential bit generation to parallel bit generation by adding a temporal dimension to the data flow. Multiple bits are generated simultaneously across different time steps through parallel tap combinations, effectively increasing the generation rate without proportionally increasing routing complexity through systematic tap allocation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If conventional tap combinations are used in parallel PRBS circuits, then the generation capability is maintained, but the number of taps required increases substantially

Engineering Contradiction:
ImprovePRBS generation capabilityVSAvoidnumber of taps
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent makes each tap combination serve multiple functions by designing tap sets that can generate multiple parallel PRBS streams simultaneously. Each tap combination is configured to contribute to multiple output streams, maximizing the utility of each tap and reducing the total number of taps needed while maintaining full PRBS generation capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent optimizes the tap combination parameters to achieve the most efficient PRBS generation. By carefully selecting and adjusting tap positions and combinations, the circuit generates multiple parallel PRBS streams with minimal taps, improving productivity while reducing the quantity of taps required compared to conventional approaches.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10673662B2Methods and circuits for generating parallel pseudorandom binary sequences
Publication Date: 2020.06.02 KEYSIGHT TECHNOLOGIES INC
  • US10673662B2 patent drawing
  • US10673662B2 patent drawing
  • US10673662B2 patent drawing

AI summary

A method for generating M parallel pseudorandom binary sequences (PRBSs), each comprising a 2n−1 sequence of pseudorandom bits, includes loading into the circuit an initial M-bit word, the initial M-bit word comprising M sequential bits selected from a pre-determined PRBS-n sequence, wherein n>1 and M>n. The method includes generating, using a plurality of logic gates of the circuit, a next M-bit word using at least n+1 of the M sequential bits of the initial M-bit word. The method includes repeatedly generating, using the logic gates of the circuit, the next M-bit word from a previous M-bit word using the at least n+1 of M sequential bits of the previous M-bit word, resulting in M parallel sequences of the PRBS-n sequence. The method includes transmitting the generated next M-bit words on an M-bit wide parallel bus.