Parallel Precoder Circuit Reducing Delay Path
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Solution Overview
Problem
Conventional parallel precoder circuits face challenges in achieving efficient operation at ultra-high speeds due to difficulties in timing adjustment and circuit complexity, particularly in optical communication systems where high-speed serial data processing requires precise timing and reduced circuit scale.
Innovation Solution
A parallel precoder circuit design that executes EXOR operations on n-row parallel inputs, utilizing a configuration of EXOR circuits and delay circuits to reduce the maximum delay path and circuit complexity, allowing for efficient operation at lower speeds while maintaining equivalent functionality to serial precoder circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a serial precoder circuit is used to process signals at ultra-high transmission speeds (10 Gbps and 40 Gbps), then the transmission speed is improved, but the operation speed requirement of the EXOR circuit becomes extremely high and timing adjustment becomes difficult
Solution Approach 1:
The patent divides the serial precoder circuit into multiple parallel EXOR circuits that process n-bit parallel data simultaneously. Each EXOR circuit operates at a reduced clock frequency of F/n Hz, where F is the original transmission speed. This segmentation allows the system to achieve ultra-high transmission speeds while each individual circuit component operates at a manageable speed, solving the timing adjustment difficulty.
2Speed
If conventional parallel precoder circuits are used to reduce operation speed requirements, then the EXOR circuit operation speed is reduced to F/n Hz, but the circuit complexity and delay path remain excessive
Solution Approach 1:
The patent reorganizes the EXOR circuits into a two-dimensional array structure with n rows and log2n columns, where circuits in the same column operate at different clock phases. This dimensional arrangement allows the maximum delay path to be reduced to log2n+1 stages while maintaining parallel processing capability. The spatial reorganization enables shorter delay paths compared to conventional linear arrangements.
3Productivity
If EXOR circuits are connected in cascade to process parallel data, then the parallel processing capability is achieved, but the maximum delay path increases and limits the operation speed
Solution Approach 1:
The patent introduces dynamic clock phase control where circuits in the same column operate at different clock phases that are sequentially activated. This dynamic timing arrangement allows data to flow through the circuit array more efficiently, reducing the effective delay path from n stages (in cascade connection) to log2n+1 stages. The dynamic phase switching optimizes the timing characteristics while maintaining parallel processing throughput.
Data Source
AI summary
A parallel precoder circuit executes an EXOR operation on an n-row parallel input, and outputs an n-row parallel output, where 2≦n. Outputs of EXOR circuits each of which having a largest column number from among EXOR circuits disposed in first to (n−1)th rows become first-row to (n−1)th-row parallel outputs, respectively. A output of an nth-row delay circuit becomes an nth-row parallel output.