Parallel Prefix-Code Decoding with Leftover-Bit Propagation
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Solution Overview
Problem
Decoding variable-length prefix codes, such as Huffman codes, is challenging due to the difficulty in parallelizing the process as the boundaries of each codeword are unknown, leading to performance limitations and increased cycles per decoded symbol.
Innovation Solution
The method involves preprocessing a stream of prefix code words to generate fixed-width code words, which are then decoded using parallel decoder circuits and subsequent stages of leftover bit propagation, allowing for parallelized decoding and reducing the dependence on prior leftover bit-counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If variable-length prefix codes are decoded using traditional sequential methods, then decoding accuracy is maintained, but decoding speed and throughput are limited due to unknown codeword boundaries
Solution Approach 1:
The patent segments the decoding process into multiple parallel stages, where each stage processes a fixed number of input bits and produces candidate decoded symbols with associated leftover bit-counts. This segmentation enables parallel processing while maintaining the ability to handle variable-length codewords by dividing the unknown boundary problem into manageable fixed-width processing units.
Solution Approach 2:
The patent introduces a new dimension by processing multiple possible leftover bit-counts simultaneously across parallel decoder circuits. Instead of sequentially determining the correct codeword boundary, the system evaluates multiple boundary possibilities in parallel and selects the valid one, effectively adding a dimensional approach to solving the variable-length decoding problem.
2Productivity
If parallel decoder circuits are used to increase throughput, then decoding speed improves, but the dependence on prior leftover bit-counts creates a critical path that limits clock cycle frequency
Solution Approach 1:
The patent performs preliminary actions by pre-computing and storing decoding results for all possible fixed-width input combinations and leftover bit-count scenarios in lookup tables. This preliminary preparation eliminates the need for sequential computation during the critical decoding path, allowing parallel circuits to simply retrieve and select results, thereby reducing iteration intervals and increasing clock frequency.
Solution Approach 2:
The patent introduces leftover bit-count propagation as an intermediary mechanism that carries state information between parallel decoding stages. This intermediary structure allows each parallel stage to operate independently with its own set of possible leftover bit-counts, breaking the sequential dependency chain while maintaining overall decoding correctness through the propagation and selection of valid states.
3Ease of operation
If fixed-length words are used instead of variable-length codewords, then parallel processing becomes feasible, but the variable-length prefix code structure is lost
Solution Approach 1:
The patent changes the parameter of input word length from variable to fixed for the purpose of parallel processing, while simultaneously maintaining the variable-length codeword semantics through multiple parallel processing paths. Each fixed-width processing path handles a specific range of codeword lengths, and the combination of all paths preserves the original variable-length prefix code structure and its unique decodability properties.
Data Source
AI summary
Methods and systems are provided for decoding variable-length codes in a parallel process. A stream of variable-length code words is divided into fixed length words. A plurality of parallel sets of decoder circuits each receive, in parallel, a current fixed length word and a prior fixed length word. Each decoder circuit has a respective fixed leftover bit-count. Each decoder circuit generates a respective output that may include a decoded symbol and a new leftover bit-count. Each respective output is determined based on the respective current fixed length word, the respective prior fixed length word, and the respective fixed leftover bit-count. A set of selected decoder circuit outputs is generated for each set of the parallel sets of decoder circuits based on a set of first leftover bit-counts. One output from each set of selected decoder circuit outputs is selected as a final output based on a second prior leftover bit-count.