Parallel Prefix Decoding for Low-Latency Huffman Tree Generation

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Solution Overview

Problem

Current data decompression techniques, particularly those using Huffman coding in DEFLATE algorithms, face significant throughput limitations due to the computational complexity of generating Huffman trees for each data block, leading to latency issues and reduced decompression performance, especially for small payloads.

Innovation Solution

The implementation of a prefix decoder engine and parallel decompression engines that utilize check-pointing and concurrent forward/reverse tree parsing approaches to accelerate Huffman tree generation, allowing multiple codes to be generated in parallel and reducing overall tree generation latency by 3×, while also enabling a single prefix decoder engine to service multiple decompressors in a round-robin configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional sequential Huffman tree generation is used, then decoding accuracy is maintained, but decompression throughput is limited and latency increases

Engineering Contradiction:
Improvedecompression throughputVSAvoidtree generation latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the Huffman tree generation process into multiple independent parallel streams (forward stream and reverse stream), each processing different portions of the code length array simultaneously. This segmentation enables concurrent execution of decoding operations that were previously sequential, directly increasing throughput while maintaining accuracy through independent verification of results

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension by implementing check-pointing mechanisms that allow the decoder to save intermediate states and resume processing. This enables parallel processing across different time checkpoints, effectively transforming a single-threaded sequential process into a multi-threaded parallel system that achieves 3x speedup

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple decompression engines are implemented, then throughput improves, but hardware area and complexity increase

Engineering Contradiction:
Improvedecompression throughputVSAvoidhardware area
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs a universal prefix decoder engine that can service multiple decompression engines through time-multiplexed operation. The single decoder engine dynamically switches between serving different decompression engines based on readiness signals, providing multi-functionality that achieves high throughput without proportionally increasing hardware area

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements preliminary preparation of code length arrays and check-point data structures before actual decoding begins. By pre-processing and organizing data in advance, the system reduces the computational burden during active decoding, allowing faster processing without requiring additional dedicated hardware for each decompression engine

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10083034B1Method and apparatus for prefix decoding acceleration
Publication Date: 2018.09.25 INTEL CORP
  • US10083034B1 patent drawing
  • US10083034B1 patent drawing
  • US10083034B1 patent drawing

AI summary

In one embodiment, an apparatus comprises a memory, a processor and a prefix decoder engine to access a plurality of code lengths of a header associated with a compressed data block; determine a number of instances of each code length of at least some of the plurality of code lengths; and operate a plurality of decode streams in parallel, a first decode stream of the plurality of decode streams to iterate through a first portion of the plurality of code lengths and determine codes corresponding to the first portion of the plurality of code lengths, a second decode stream of the plurality of decode streams to iterate through a second portion of the plurality of code lengths and determine codes corresponding to the second portion of the plurality of code lengths.