Parallel Preprocessor Image Signal Segmentation for Bottleneck Resolution

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Solution Overview

Problem

Processing large images in real-time is challenging due to the bottleneck phenomenon caused by entropy coding, leading to waiting times and increased circuit costs when using multiple decoders.

Innovation Solution

An image processing apparatus with parallel preprocessors and a storage system that generates and stores intermediate signals, allowing for independent processing and reducing circuit costs while maintaining high-speed image processing, including binary arithmetic coding and adaptive section sizing for efficient image processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single decoder is used for entropy coding, then circuit cost is reduced, but processing speed decreases due to bottleneck phenomenon and waiting time

Engineering Contradiction:
Improvecircuit costVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The image signal is divided into multiple sections, with each preprocessor handling a specific section in parallel. This segmentation allows the system to process multiple sections simultaneously, improving overall processing speed while maintaining a reasonable number of decoders.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential processing (single dimension) to parallel processing across multiple dimensions by introducing multiple preprocessors that operate simultaneously on different sections of the image signal, effectively adding a temporal parallelism dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple decoders are employed to increase processing speed, then productivity is improved, but device complexity and circuit cost increase

Engineering Contradiction:
Improveprocessing speedVSAvoidcircuit cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The image signal is divided into multiple sections, with each preprocessor handling a specific section in parallel. This segmentation allows the system to process multiple sections simultaneously, improving overall processing speed while maintaining a reasonable number of decoders.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The preprocessors perform preliminary processing on different sections of the image signal before the data reaches the decoder. This preliminary action prepares the data in advance, allowing the decoder to work more efficiently and reducing the overall processing time without requiring multiple full decoders.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If section size is increased to improve processing throughput, then productivity increases, but waiting time in postprocessor increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidwaiting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The section size is dynamically adjusted based on the processing capabilities of the preprocessors and postprocessor. The controller monitors the system state and adapts the section size to optimize the balance between throughput and waiting time, ensuring efficient utilization of all components.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The controller uses feedback from the processing speeds of preprocessors and postprocessor to adjust the section size. This feedback mechanism ensures that the system adapts to varying processing conditions, maintaining optimal performance by preventing both bottlenecks and resource underutilization.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11463699B2Image processing apparatus and control method thereof
Publication Date: 2022.10.04 SAMSUNG ELECTRONICS CO LTD
  • US11463699B2 patent drawing
  • US11463699B2 patent drawing
  • US11463699B2 patent drawing

AI summary

The disclosure relates to an image processing apparatus, the image processing apparatus including: an image signal receiver configured to receive an image signal; a first preprocessor configured to sequentially processes a predetermined section of the received image signal and generate a first intermediate signal; a second preprocessor arranged in parallel with the first preprocessor and configured to sequentially process another section of the image signal and generate a second intermediate signal; a storage configured to store the first intermediate signal and the second intermediate signal; and a postprocessor configured to perform signal processing with regard to the first and second intermediate signals stored in the storage, the size of the section being corresponding to processing speeds of the first and second preprocessors and a processing speed of the postprocessor.