Parallel Priority Queue on GPGPU Using Barrier Synchronization
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Solution Overview
Problem
The development of an efficient parallel priority queue on general-purpose graphics processing units (GPGPUs) is hindered by the inefficient implementation of locks and single instruction, multiple thread (SIMT) architecture, preventing certain applications from running effectively on these powerful computing platforms.
Innovation Solution
A parallel priority queue is implemented using a parallel heap data structure, where insert and removal operations are performed in parallel, with synchronization achieved through barriers, and kernel functions are executed in a pipelined fashion to maintain the heap property, allowing for concurrent execution on GPGPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If locks are implemented for synchronization in a parallel priority queue on GPGPUs, then thread safety is improved, but execution efficiency deteriorates due to inefficient lock implementation on GPGPU architecture
Solution Approach 1:
The patent extracts the synchronization function from traditional lock mechanisms and implements it through barrier synchronization at specific points in the parallel algorithm. This removes the inefficiency of locks while maintaining thread safety through coordinated synchronization events at critical sections of the parallel priority queue operations.
Solution Approach 2:
The patent introduces barrier synchronization as an intermediary mechanism between threads operating on the parallel priority queue. Instead of using locks that block threads, barriers coordinate threads at synchronization points, allowing efficient parallel execution while maintaining data integrity through the mediator barrier mechanism.
2Productivity
If parallel operations are implemented on GPGPUs, then processing throughput is improved, but maintaining heap property becomes more difficult due to SIMT architecture constraints
Solution Approach 1:
The patent segments the parallel priority queue operations into distinct phases (insertion phase, deletion phase, heapification phase) that can be executed in parallel using SIMT architecture. Each phase maintains heap properties through localized operations that are then combined, reducing the complexity of maintaining global heap invariants across all threads simultaneously.
Solution Approach 2:
The patent performs preliminary actions by pre-allocating memory structures and pre-synchronizing threads at barrier points before executing parallel heap operations. This preliminary setup simplifies the maintenance of heap properties during parallel execution by ensuring all threads start from a known valid state and follow predetermined operation sequences.
3Device complexity
If sequential priority queue operations are used, then implementation simplicity is maintained, but execution time increases significantly on multi-core and many-core processors
Solution Approach 1:
The patent transforms the static sequential priority queue into a dynamic parallel structure that adapts to the GPGPU architecture. The dynamic parallel heap allows operations to be executed concurrently across multiple threads while maintaining correctness through barrier synchronization, achieving both improved execution time and reasonable implementation complexity.
Solution Approach 2:
The patent changes the operational parameters of the priority queue by implementing parallel insertion and deletion operations that operate on multiple elements simultaneously. This parameter change from sequential to parallel operations reduces execution time on multi-core processors while the use of standard barrier synchronization keeps the implementation complexity manageable.
Data Source
AI summary
Disclosed are various embodiments for a parallel priority queue implemented on one or more many-core processors and/or multi-core processors such as those in general-purpose graphics processing units (GPGPUs). According to various embodiments, a priority may be determined according to a timestamp of an item, such as an event or an entry, in a priority queue. A priority queue interface may comprise functions to insert and remove entries from the priority queue. Priority order of the entries may be maintained as the entries are inserted and removed from the queue.