Parallel Processing Apparatus with Flow-Based Queue Mapping

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing parallel processing techniques in multiprocessor or multi-core environments fail to maintain data order and provide effective processor scaling based on network traffic conditions, leading to data re-ordering issues.

Innovation Solution

An apparatus and method for parallel processing that includes a mapper to classify data into flows, a queue memory to store pointers, and a distributor to transmit data to processors, with a flow table for dynamic queue management and processor assignment based on traffic conditions, ensuring data order is maintained and processor scaling is achieved without re-ordering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If dynamic receive queue balancing (DRQB) technique is used to provide processor scaling based on traffic amount, then processor scaling capability is improved, but data re-ordering occurs during the scaling process

Engineering Contradiction:
Improveprocessor scaling capabilityVSAvoiddata order maintenance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system segments data processing by introducing queue structures that separate data buffering from processing. Each queue maintains data order independently while processors can be dynamically assigned to different queues based on traffic conditions, thus preventing data re-ordering during processor scaling.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The queue structure acts as an intermediary between data sources and processors. Data is first placed in queues in order, then processors are assigned to queues dynamically. This intermediary layer decouples the data flow from processor assignment changes, eliminating re-ordering issues while maintaining adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If fixed processor mapping for flows is used in RSS techniques, then data order is maintained, but processor scaling according to network traffic conditions cannot be provided

Engineering Contradiction:
Improvedata order maintenanceVSAvoidprocessor scaling capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The system introduces dynamic queue assignment where processors can be reassigned to different queues based on real-time traffic conditions. The queue structures remain stable to maintain data order, while the mapping between processors and queues becomes dynamic, allowing processor scaling without compromising data ordering.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system adds a queue dimension between data flows and processors. Instead of directly mapping flows to processors in fixed or dynamic ways, flows are first mapped to queues which then map to processors. This additional dimension allows independent optimization of data ordering (at queue level) and processor utilization (at processor level).

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10142245B2Apparatus and method for parallel processing
Publication Date: 2018.11.27 ELECTRONICS & TELECOMM RES INST
  • US10142245B2 patent drawing
  • US10142245B2 patent drawing
  • US10142245B2 patent drawing

AI summary

An apparatus for parallel processing according to an example may include a queue memory configured to store one or more queues, a data memory configured to store data, a mapper configured to classify the data into flows and store a pointer of the data in a queue mapped with the flow; a plurality of processors configured to perform a process based on the data; and a distributor configured to extract the data from the data memory by referring to the pointer stored in the queue and transmit the data to the processor, wherein the distributor transmits data corresponding to a single queue to a single processor.