Parallel Processing Architecture Memory Block Transfers
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Solution Overview
Problem
Current processing architectures are ill-suited for handling large and complex projects, particularly in managing and processing vast amounts of disparate data, leading to inefficiencies and increased resource requirements.
Innovation Solution
A parallel processing architecture with memory block transfers, where an array of compute elements is accessed and controlled on a cycle-by-cycle basis using wide control words generated by a compiler, enabling autonomous memory block transfers that support data movement between cache and memory systems, allowing for efficient processing of tasks and subtasks without interrupting ongoing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data movement is performed through the array of compute elements, then data can be transferred between cache and memory systems, but the processing operations are interrupted and throughput is reduced
Solution Approach 1:
The system separates data movement operations from compute operations by introducing dedicated memory block transfer control logic that operates independently from the array of compute elements. This segmentation allows data transfers to occur through dedicated pathways without interrupting the compute pipeline, resolving the contradiction between data movement capability and processing throughput.
Solution Approach 2:
The patent introduces memory block transfer control logic as an intermediary component that handles data movement between cache and memory systems. This intermediary operates autonomously from the compute elements, enabling data transfers to proceed without blocking processing operations, thus maintaining high throughput while facilitating ease of data movement.
2Productivity
If fine-grained control of compute elements is implemented using cycle-by-cycle control words, then processing efficiency is improved, but control logic complexity increases
Solution Approach 1:
The patent employs universal control words that can direct multiple types of operations including compute operations, memory accesses, and inter-element data transfers. This multi-functionality reduces control logic complexity by consolidating diverse control functions into a single standardized interface, while maintaining fine-grained cycle-by-cycle control for high processing efficiency.
Solution Approach 2:
The control logic is designed to automatically generate and manage control words for data movement operations without requiring external intervention. The memory block transfer control logic autonomously handles the complexity of coordinated data transfers, freeing higher-level control structures from managing low-level details, thus improving efficiency without proportionally increasing overall system complexity.
3Productivity
If autonomous memory block transfers are implemented outside the array, then data movement occurs without interrupting processing, but additional control logic is required
Solution Approach 1:
The patent merges the control functions for compute operations and memory block transfers into a unified control architecture. The same control word interface and control logic structures used for compute operations are extended to also manage autonomous memory transfers, eliminating the need for separate complex control logic while enabling processing continuity during data movements.
Data Source
AI summary
Techniques for task processing based on a parallel processing architecture with memory block transfers are disclosed. An array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. Control for the array is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. A control word from the stream of control words includes a source address, a target address, a block size, and a stride. Memory block transfer control logic is used. The memory block transfer logic is implemented outside of the array of compute elements. A memory block transfer is executed. The memory block transfer is initiated by a control word from the stream of wide control words. Data for the memory block transfer is moved independently from the array of compute elements.