Parallel Processing Device With Multi-Mode Preprocessing Units

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Solution Overview

Problem

Existing parallel processing devices have inefficiencies due to separate units for multiplication and summation operations, leading to underutilization of processing units and difficulties in data exchange, which limits overall performance.

Innovation Solution

A parallel processing device design that integrates preprocessing units with selection and shift operators, allowing each unit to perform both multiplication and summation operations, and facilitates data exchange between units, enabling flexible operation modes without significant hardware complexity increase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate units for multiplication and summation operations are used, then the device structure is simple and clear, but the processing units are underutilized and overall performance is limited

Engineering Contradiction:
Improveprocessing unit utilization efficiencyVSAvoiddevice structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by designing processing units that can perform both multiplication and summation operations. Each processing unit includes a preprocessing part with a selection operator and a shift operator, allowing the same unit to dynamically switch between multiplication mode (using shift operator) and summation mode (using selection operator), thereby eliminating the need for separate dedicated units and improving utilization efficiency

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges previously separate multiplication and summation units into a single integrated processing unit. By combining the preprocessing part with both selection and shift operators, the patent consolidates multiple functions into one unit, reducing hardware redundancy while maintaining the capability to perform both operation types efficiently

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If data exchange between processing units is restricted, then the hardware complexity is reduced, but the overall performance of the parallel processing device is limited

Engineering Contradiction:
Improveoverall device performanceVSAvoiddata exchange mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments data exchange functionality into standardized input and output interfaces for each processing unit. Each unit has defined data input terminals and output terminals with standardized connection protocols, allowing modular data exchange that simplifies the overall system architecture while enabling flexible inter-unit communication for improved performance

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240004667A1Parallel processing device
Publication Date: 2024.01.04 MORUMI CO LTD
  • US20240004667A1 patent drawing
  • US20240004667A1 patent drawing
  • US20240004667A1 patent drawing

AI summary

A parallel processing device includes a preprocessing part comprising preprocessing units and a main processing part comprising summers. Each of the preprocessing units comprises a selection operator and a shift operator. The selection operator is configured to operate when corresponding one of the preprocessing units operates in a summing mode, and configured to perform a function of transmitting corresponding some first signals of first signals to corresponding one of the summers according to bits of corresponding one of second signals respectively. The shift operator is configured to operate when the corresponding preprocessing unit operates in a multiplication mode, and configured to transmit signals resulting from shifting corresponding one of the first signals to the corresponding summer according to the bits respectively.