Parallel Processing Architecture with Shallow Pipeline
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Solution Overview
Problem
Existing data processing architectures are often ill-suited or inflexible for handling complex processing jobs, such as those involving large datasets, leading to inefficiencies in task processing and throughput.
Innovation Solution
A highly parallel processing architecture with a shallow pipeline is implemented using a two-dimensional array of compute elements, where control is provided on a cycle-by-cycle basis through variable length microcode control words generated by a compiler, enabling parallel execution and selective enabling/disabling of compute elements to optimize task processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional data processing architecture is used, then the system structure is simple, but the task processing efficiency and throughput are insufficient for complex processing jobs
Solution Approach 1:
The processing architecture is segmented into a two-dimensional array of compute elements, where each element can be independently controlled and configured. This segmentation allows parallel processing of multiple tasks simultaneously, dramatically improving throughput for complex data processing jobs while maintaining manageable complexity through modular organization.
Solution Approach 2:
The architecture transitions from traditional one-dimensional or hierarchical processing structures to a two-dimensional array configuration. This dimensional change enables simultaneous access and processing from multiple directions, enhancing data flow efficiency and compute element utilization for complex processing tasks.
2Adaptability or versatility
If control is provided on a cycle-by-cycle basis with variable length microcode control words, then the adaptability for different processing tasks is improved, but the control complexity increases
Solution Approach 1:
The control mechanism uses dynamic variable-length microcode control words that can be adjusted based on the specific processing task requirements. This dynamic control allows the same hardware architecture to adapt to diverse processing tasks efficiently, achieving high versatility without requiring multiple specialized systems.
Solution Approach 2:
The control word length and format are changed as parameters based on the processing task being executed. By varying control word parameters dynamically, the system achieves adaptability for different topologies and processing requirements while using a unified control mechanism, balancing versatility and complexity.
3Productivity
If multiple compute elements are enabled simultaneously for parallel execution, then the throughput is improved, but the power consumption increases
Solution Approach 1:
Instead of enabling all compute elements simultaneously, the architecture enables only the necessary subset of compute elements required for the current processing task. This partial action approach maintains high throughput by activating sufficient processing units while avoiding the excessive power consumption that would result from enabling the entire array.
Solution Approach 2:
The control mechanism enables and disables compute elements in periodic cycles based on task requirements, allowing the system to switch between different configurations efficiently. This periodic control optimizes the balance between throughput and power consumption by activating compute elements only when needed for specific processing phases.
Data Source
AI summary
Techniques for task processing using a highly parallel processing architecture with a shallow pipeline are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, microcode control words generated by the compiler. Relevant portions of the control word are stored within a cache associated with the array of compute elements. The control words are decompressed. The decompressing occurs cycle-by-cycle out of the cache over multiple cycles. A compiled task is executed on the array of compute elements, based on the decompressing. Simultaneous execution of two or more potential compiled task outcomes is provided.