Parallel Processor Data-Vector Generation Unit
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Solution Overview
Problem
Conventional SIMD processors are inefficient in fetching and processing full coefficient vectors, leading to wasted memory storage, additional instruction cycles, and pipeline stalls, which reduce processing capacity.
Innovation Solution
A parallel processor with a data-vector generation unit that receives a first vector and a control vector to generate a second vector with more elements, allowing for operations like duplication, negation, and constant assignment, thereby eliminating the need for full vector storage and reducing instruction cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the full coefficient vector is stored in memory, then the coefficient vector is readily available for processing, but memory storage capacity and memory bandwidth are wasted
Solution Approach 1:
The patent extracts only the necessary minimal information (real number R and imaginary number I) from the full coefficient vector and stores this compressed representation in memory. The full coefficient vector is generated on-demand by the data-vector generation unit using these minimal stored values, thereby eliminating the need to store the complete vector while maintaining availability when needed.
Solution Approach 2:
The patent performs preliminary compression of the coefficient vector by storing only the essential parameters (R and I) before processing. The data-vector generation unit then generates the full coefficient vector in advance or on-demand using these pre-stored minimal values, avoiding the need to store the complete vector in memory.
2Quantity of substance
If only coefficient R and I are stored in memory, then memory storage capacity is saved, but additional instruction cycles are required to generate the full coefficient vector
Solution Approach 1:
The data-vector generation unit automatically generates the full coefficient vector using the stored minimal values (R and I) without requiring additional software instructions to perform the generation. The hardware unit self-services by interpreting the control vector and computing the full coefficient vector directly, eliminating the need for manual software intervention and additional instruction cycles.
Solution Approach 2:
The patent replaces the software-based coefficient vector generation process with a hardware data-vector generation unit that performs the generation operation in parallel. This substitution of software instructions with dedicated hardware logic eliminates the time penalty associated with software-based generation while maintaining memory efficiency.
3Reliability
If the pipeline is stalled to await generation of the full coefficient vector, then the full coefficient vector can be generated accurately, but bubbles are created in the pipeline reducing processing capacity
Solution Approach 1:
The data-vector generation unit generates the full coefficient vector in advance or in parallel with other pipeline operations, rather than waiting for software instructions to complete. This preliminary or concurrent generation eliminates the need to stall the pipeline, maintaining continuous data flow and preventing bubble creation while ensuring accurate coefficient vector generation.
Solution Approach 2:
The patent replaces the sequential software-based coefficient vector generation with a parallel hardware data-vector generation unit that operates independently of the instruction pipeline. This substitution allows the pipeline to continue executing instructions without stalling, as the hardware unit generates the full coefficient vector in parallel, thereby eliminating bubbles and maintaining maximum processing capacity.
Data Source
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AI summary
A parallel processor (10) having a plurality of parallel computational lanes (L0-L7). The parallel processor (10) comprises a data-vector generation unit (40). The data-vector generation unit comprises a first input port (50) for receiving a first vector of data elements from a memory unit (30) and a second input port (60) for receiving a control vector. The data-vector generation unit further comprises an output port (70) for outputting a second vector of data elements to the plurality of parallel computational lanes (L0-L7). The second vector comprises more data elements than the first vector. The data-vector generation unit (40) is adapted to generate the data elements of the second vector based on the data elements of the first vector and the control vector. A method of operating the parallel processor (10) is also disclosed.