Parallel Processor System Reducing Memory Latency
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Solution Overview
Problem
Memory latency significantly slows down the performance of applications, particularly in server-based verification platforms, where the serialization of highly parallel designs by control flow processors exacerbates memory access issues, leading to inefficient execution and prolonged processing times.
Innovation Solution
A parallel processor system combining control flow and data flow processing, with a test bench processor and design processor operating in parallel, utilizing a runtime events insertion and control unit, and employing a Montana Instruction Set Architecture (MISA) with multiple processing cores and dedicated memory systems to minimize memory latency and optimize data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a control flow processor is used to execute verification applications, then the processor can handle sequential instructions, but memory access latency increases significantly
Solution Approach 1:
The system segments the verification application into two distinct processing streams: a control flow processor handles testbench execution while a data flow processor handles design verification. This segmentation allows each processor to operate independently with optimized memory access patterns, reducing overall memory latency by eliminating sequential dependencies between control and data processing.
Solution Approach 2:
The patent transitions from a single-dimensional control flow processing model to a two-dimensional processing architecture combining control flow and data flow processing. The data flow processor operates in parallel with the control flow processor, adding a temporal dimension of concurrent execution that reduces memory access latency by processing data as soon as it becomes available rather than waiting for sequential instruction completion.
2Adaptability or versatility
If a typical server platform with standard CPU and memory hierarchy is used, then the system can run verification applications, but performance is slowed down by memory latency
Solution Approach 1:
The verification platform is segmented into specialized processing units: a control flow processor for testbench management and a data flow processor for design verification. This segmentation enables each unit to be optimized for its specific function, with the data flow processor featuring dedicated memory structures that eliminate general-purpose memory hierarchy overhead, thereby improving processing speed while maintaining application versatility.
Solution Approach 2:
The patent introduces a runtime event insertion and control unit that acts as an intermediary between the control flow processor and data flow processor. This intermediary manages data exchange and synchronization efficiently, reducing the need for frequent main memory accesses by keeping relevant data in intermediate buffers, thus improving productivity without sacrificing adaptability.
3Ease of manufacture
If the design is serialized by a simulator application program, then the design can be executed on standard processors, but the parallelism of the design is lost and memory latency increases
Solution Approach 1:
Instead of serializing the parallel design to fit control flow processors, the patent inverts the approach by using a data flow processor that naturally executes parallel operations. The compilation process generates data flow instructions that preserve the inherent parallelism of the design, allowing simultaneous evaluation of multiple design elements without serialization overhead, thereby improving execution efficiency while maintaining ease of manufacture through standard compilation tools.
Solution Approach 2:
The patent replaces the mechanical serialization process with a data flow execution model. Rather than forcing parallel design elements into sequential execution slots, the system substitutes the control flow mechanism with data-driven activation signals that trigger parallel operations automatically when dependencies are satisfied, eliminating the productivity loss associated with serialization while keeping the compilation process straightforward.
4Reliability
If frequent memory accesses are required to fetch data operands, then the verification can be performed, but the run time speed is substantially slowed down
Solution Approach 1:
The data flow processor architecture performs preliminary actions by pre-fetching and caching data operands into on-chip memory structures before they are needed for verification operations. The runtime event insertion unit proactively manages data movement, ensuring that required operands are available in fast memory when execution reaches that point, thereby maintaining verification reliability while reducing run time speed loss from memory latency.
Data Source
AI summary
A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit.