Parallel Processor Packet Processing via Shared Memory Semaphores

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current parallel processing systems face inefficiencies in communication between compute nodes and graphics processing units (GPUs), particularly in processing packets in real-time, which hinders effective data processing and transmission.

Innovation Solution

The system employs one or more graphics processing units (GPUs) to detect and process packet data stored in memory, utilizing shared memory portions and semaphores for communication between CPUs, GPUs, and network interfaces to manage data processing and transmission efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If parallel processing systems use traditional communication techniques between compute nodes and GPUs, then system stability is maintained, but processing speed and real-time packet handling capability deteriorate

Engineering Contradiction:
Improvepacket processing speedVSAvoidcommunication system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces shared memory as an intermediary between CPU and GPU, allowing direct data exchange without traditional complex communication protocols. The semaphore mechanism acts as a simple mediator for synchronization, replacing elaborate inter-process communication systems and enabling faster packet processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The communication system is segmented into independent functional components: shared memory for data exchange, semaphores for synchronization, and event-driven notification mechanisms. This segmentation simplifies each component while maintaining overall system functionality and improving processing speed.

Inventive Principle:
Principle #1Segmentation

2Productivity

If GPUs process packets independently in real-time, then productivity is improved, but communication coordination between processors worsens

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidcommunication coordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The GPU is empowered to independently detect packet availability in shared memory and process packets autonomously without continuous CPU intervention. The event-driven architecture allows the GPU to self-manage its processing queue, improving productivity while reducing coordination overhead through the simple semaphore mechanism.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements event-driven feedback where the GPU notifies the CPU through semaphores when packets are processed or when shared memory needs replenishment. This feedback mechanism enables autonomous GPU operation while maintaining simple coordination through standardized notification protocols.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If shared memory and semaphores are used for communication, then ease of operation is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmission managementVSAvoidmemory and synchronization structure
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

Shared memory serves multiple functions simultaneously: data storage, data exchange between CPU and GPU, and triggering event notifications. Semaphores provide universal synchronization and coordination across different processing operations. This multi-functionality simplifies operation by using standardized mechanisms for diverse communication needs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4336372A1Using parallel processor(s) to process packets in real-time
Publication Date: 2024.03.13 MELLANOX TECHNOLOGIES LTD(IL)
  • EP4336372A1 patent drawingFigure 1
  • EP4336372A1 patent drawingFigure 2
  • EP4336372A1 patent drawingFigure 3

AI summary

Apparatuses, systems, and techniques of using parallel processor(s), such as one or more graphics processing units, to process packets (e.g., in real time). In at least one embodiment, a processor (e.g., a parallel processing unit, a central processing unit, and/or the like) detects when packet data has been stored in a memory accessible by the parallel processing unit. Then, the parallel processing unit may process the packet data to produce output data.