Parallel Processor Architecture With Dynamic PE Allocation
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Solution Overview
Problem
Existing processor architectures, particularly MIMD, suffer from inefficiencies due to high rates of 'dark silicon' where processing elements remain unused, leading to increased costs and inefficiency across various use cases.
Innovation Solution
A processor architecture featuring a flexible allocation mechanism for processing elements (PEs) that allows decoupling from fixed instruction slots, enabling dynamic assignment and aggregation, supported by a compiler that optimizes instruction allocation to minimize dark silicon and enhance flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MIMD architecture with multiple instruction slots is used to process multiple instruction streams in parallel, then processing power and efficiency for certain use cases is improved, but the rate of dark silicon increases to above 90% of total processing elements
Solution Approach 1:
The patent implements dynamic allocation of processing elements to instruction slots, where PEs are not fixed to specific slots but can be reassigned based on runtime conditions. The allocation unit dynamically determines which PEs should execute which instructions, allowing the system to adapt to varying workload requirements and minimize dark silicon by keeping PEs actively utilized across different instruction streams.
Solution Approach 2:
Processing elements are designed to be universal and not dedicated to specific instruction slots. Each PE can execute any instruction type (scalar, vector, matrix operations) by receiving appropriate configuration signals. This multi-functionality allows PEs to be flexibly assigned to different instruction slots based on computational needs, preventing the high dark silicon rates that occur when PEs are specialized and idle for certain operation types.
2Productivity
If processor is designed with thousands of multipliers and multiple instruction slots for optimized performance, then efficiency for target use cases is improved, but area of dark silicon increases and time it is kept dark increases
Solution Approach 1:
The system employs dynamic PE allocation where the allocation unit continuously assigns PEs to instruction slots based on current computational demands. This dynamic reassignment ensures that the large array of PEs (thousands of multipliers) remains actively utilized across different workloads, reducing the area and time of dark silicon compared to static allocation schemes where PEs would remain idle for extended periods.
Solution Approach 2:
The patent changes the operational parameters of PEs by allowing them to switch between different operation modes (scalar, vector, matrix) and different data types based on incoming instructions. This parameter flexibility ensures that the processor can efficiently handle diverse computational tasks without leaving PEs idle, thereby reducing dark silicon area and duration while maintaining high efficiency across various use cases.
3Device complexity
If fixed assignment of processing elements to instruction slots is used, then implementation simplicity is improved, but flexibility and adaptability to different use cases deteriorates
Solution Approach 1:
The patent introduces dynamic allocation mechanisms that allow PEs to be reassigned to different instruction slots based on runtime conditions. The allocation unit receives instructions and determines optimal PE assignments, enabling the system to adapt to various use cases (matrix operations, vector processing, scalar computations) while maintaining a relatively simple hardware structure. This dynamic approach provides flexibility without significantly increasing implementation complexity.
4Productivity
If processing elements are allocated to minimize dark silicon, then processor utilization efficiency is improved, but complexity of allocation control increases
Solution Approach 1:
The allocation unit performs preliminary assignment of PEs to instruction slots before execution begins. By pre-configuring which PEs should handle which instructions based on the incoming workload, the system minimizes dark silicon without requiring complex real-time control during execution. This preliminary action approach simplifies the control complexity while maintaining high processor utilization efficiency.
Data Source
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AI summary
A processor comprising: a program memory for storing instructions; a decoder adapted to convert the instructions into respective operation codes and enable signals; a controller including an instruction word consisting of a plurality of instruction slots for providing the instructions to the decoder; a plurality of processing elements, each processing element being configured to operate during a time slot in accordance with an operation code provided to an input of the considered processing element so as to apply a mathematical operation to an input data element and generate an output data element, wherein an instruction provided via an instruction slot identifies one or more target processing elements to be used for executing the considered instruction, wherein the enable signals are adapted to control assignment of the operation codes to the processing elements; interconnection circuitry adapted to provide any of the operation codes to any of the processing elements at each time slot and configured to be operated in accordance with the enable signals.